Sony STR-DB900 Service Manual page 38

STR-DB900
Pin No. Pin Name
50 PAGE2
51 VSS
52, 53 PAGE1, PAGE0
54 BOOT
55 TST1
56 BST
57 MOD1
58 MOD0
59 EXLOCK
60 VDDI
61 VSS
62, 63 A17, A16
64 to 66 A15 to A13
67 GP10
68 GP9
69 GP8
70 VDDI
71 VSS
72 to 75 D15/GP7 to D12/GP4
76 VDDE
77 to 80 D11/GP3 to D8/GP0
81 VSS
82 to 85 A9, A12 to A10
86 TDO
87 TMS
88 XTRST
89 TCK
90 TDI
91 VSS
92 to 97 A8 to A3
98, 99 D7, D6
100 VDDI
101 VSS
102 to 105 D5 to D2
106 VDDE
107, 108 D1, D0
109, 110 A2, A1
111 VSS
112 A0
113 PM
114 SDI3
115 SDI4
116 SYNC
117 TST2
118 GP11
119 TST3
120 VDDI
38
I/O
O Not used. (Open)
— Ground
O Not used. (Open)
I Not used. (Connected to ground.)
I Not used. (Open)
I Boot strap signal input
I Operation mode setting pin Connected to VDD
I Operation mode setting pin Connected to ground
I PLL lock error signal and data error flag input
— Power supply (+2.5 V)
— Ground
O Address signal output Not used. (Open)
O Address signal output to DRAM
— Not used. (Open)
I/O Audio signal input/output to MB91354APMT
I Channel status bit 1 input from LC89056W
— Power supply (+2.5 V)
— Ground
I/O DRAM data input/output
— Power supply (+3.3 V)
I/O DRAM data input/output
— Ground
O Address signal output to DRAM
O Not used. (Open)
I Not used. (Open)
I Not used. (Open)
I Not used. (Open)
I Not used. (Open)
— Ground
O Address signal output to DRAM
I/O DRAM data input/output
— Power supply (+2.5 V)
— Ground
I/O DRAM data input/output
— Power supply (+3.3 V)
I/O DRAM data input/output
O Address signal output to DRAM
— Ground
O Address signal output to DRAM
I PM signal input from MB91354APMT
I Audio serial data input
I Not used. (Connected to ground.)
I Sync/non-sync setting pin ("L": sync, "H": non-sync) Connected to VDD
— Not used. (Connected to ground.)
— Not used. (Open)
— Not used. (Connected to ground.)
— Power supply (+2.5 V)
Description