Hpi Bus Multiplexer; Codec - E.F. Johnson Company 5100 ES Series Service Manual

Circuit Description
5.5.3
The DSP communicates with the MPC870 processor on the UI Board via its 16 bit host
peripheral (HPI) bus. This interface is used by the MPC870 to load application code into
the DSP internal SRAM and for exchanging control/status with the DSP.
Due to pin limitations on the 60 connector (J2) between the UI and Logic board, the HPI
bus is multiplexed across J2 in two 8 bit transfers. The bus transfer is controlled by logic in
the CPLD at U20. The signals controlling the transfer (HDS1, HDS2, H_nCS, and H_R/
nW – J2 pins 39, 50, 12 and 13) are generated by the MPC870. Operation of the
multiplexer logic is shown in the table below.
H_nCS
1
0
0
0
0
5.5.4
The Codec (U27) is a support chip for the DSP. It provides the A/D and D/A conversion
between the DSP and the microphone and speaker audio signals and between the DSP and
the RF Deck modulation signals.
The operation of the Codec is determined by fourteen internal registers. These registers are
configured by the MPC870 on the UI Board via the Codec I
internal timing is derived from a 12.288 Mhz TCXO (Y2).
The interface to the DSP (U15) is via an SSI bus. The Codec generates the framing and
clock signals for this bus as configured by the MPC870 via the I
bus clock (signal CODEC_CLK) is set to 768 KHz with a frame time (signal CODEC_FS)
of 24 KHz.
5-22 5100 ES Series Portable Radio Service Manual

HPI Bus Multiplexer

H_R/nW HDS1
x x
1 0
1 1
0 0
0 1

Codec

HDS2 8 bit bus J2
x Hi Z
1 DSP lsb
0 DSP msb
1 PPC lsb
0 PPC msb
2
C bus interface. The Codec
2
C control bus. The SSI
January 2007