Onkyo TX-RZ830 Service Manual page 86

1
HDBT SECTION
BAHDM-2424(4/8)
E
TP9620
TP9621
TP9622
TP9623TP9624
TP9617
+3.3V
TP9618
R9728
D 1k
TP9619
SPI MEMORY
GNDDG
32Mbit
R9729
220
1
/CS
2
DO
R9730 3
IO2
220
4
GND
R9731
47k
W25Q32JVSSIQ
GNDDG
HDBaseT SPI MEMORY
C
HDBaseT CLOCK
Q9615
1 VCC 4
OE
2 GND OUT 3
BK1005LL241-T
DSO321SR-AA-125MHz-100
125MHz/CMOS
125MHz/LVDS
1
OE VCC
2
NC OUTN
3
GND OUTP
Q9616
GNDDG DSO323SJ-AAC-125MHz
B
A
1
2
MOSI_M
MSCK_M
MISO_M
SPI_SELECT
MCS_M
Q9618 +3.3V
TC74LCX125FT(EL_K)
C9703
104K 16V
1 1 VCC 14
2 2 13
13
3 3 12
12
4 4 11
11
5 5 10
10
+3.3V
6 6 9
9
7 GND 8
8
R9741
1k
8
VCC C9697 GNDDG
7
MCS_M
104K 16V
IO3
6 MSCK_M MSCK_M
CLK
5
MOSI_M
DI
R9738
Q9617
220
R9739
220
MISO_M
MCS_M
+3.3V
L9616
L200:
LBC2518T100M
10uH(+/-20%)
375mA/0.36ohm
C9699 CHIP TANTAL
226M C9700
6.3V 100u 10V
CASE-C
C9696
104K 16V
R9747
GNDDG
L9615 0 RCB_P
R9737 C9701 R9748
1178mV
150 103K 0
RCB_N
1052mVpp
C9698
104K 16V
6 R9749
0
5
OSC_125N
4 OSC_125P
R9750
0
GNDDG
2
3
+3.3V
Y3
WAKEUP_IN
R9404 1k W3
WAKEUP_OUT_ST9
ST9
R9405 10k
R9406 1k C20
POR_BYPASS
R9407 1k
'0' - POR enabled C9704 102K
'1' - POR disabled R9414 0
D15
RESET_N
+3.3V
R9408 1k
ST8
Q9619 R9409 10k
DTC014EEBTL
R9410 1k
ST7
R9411 1k
GNDDG
R9415 0
B20
R9412 1k
RESET_IN
ST6
R9413 1k
MCS W4
R9416 220
EE_CS_ST8
MSCK
R9417 220 V4
EE_SCL_SCK
MISO
R9418 220 Y4
EE_SDA_MI
MOSI U4
R9419 220
EE_MO_ST7
'0' - Osc.
'1' - Crystal
R9402 1k
R9403 1k V3
XO25M_SEL
GNDDG
W1
RCB_REFCLK0_M
W2
RCB_REFCLK0_P
Y2
XO25MHZ_XIN
Y1
XO25MHZ_XOUT
GNDDG
3
4 5
Schematic Diagrams
MISC
VS2000TX
Q9610 G
T4
IPU TDI
IPU
R4
TDO
M4
TCK
IPU
N4
TRST P4
IPD
TMS
IPU
U5
PMS_TX
DBG_TXD_ST6
IPU
U8
PMS_RX
DBG_RXD
IPU
U9
R9424 47 HOST_SCL
CFG_SCL
IPU
U10 R9425 47 HOST_SDA
CFG_SDA
IPU
U7
R9426 47
IPU I2C1_SCL_MST
U6 R9427 47
I2C1_SDA_MST
IPU
U14
I2C2_SCL_MST
IPU
U13
IPD I2C2_SDA_MST
IPU
IPU
U12 R9432 47
IPU I2C_SCL_SLVI
IPU
U11
R9433 47
IPU
I2C_SDA_SLV
IPD
V2
FU_V2
V1 R9429 27k
FU_V1
IPD
R9430 27k
D19
FU_D19
GNDDG
C19
IPD FU_C19
+3.3V
GNDDG
GNDPOH
GNDDG
GND_CHASSIS
reference 1A
*P9606 NEJITANSI ST3
4 5
6
RESET_N
for Debug/FW Update
RS232C IF
PMS_TX
PMS_RX
HOST_SCL
HOST_SDA
VS2_I2C1_SCL_MSTR_TO_BOT
VS2_I2C1_SDA_MSTR_TO_BOT
+3.3V
To REAR PANEL
TP9628
TP9629
1 2 3 4
GND_CHASSIS
P9605
TER21-0130V
TP9627
1 2 3 4
GNDDG
*P9606
NEJITANSI ST3
DRX-4.2/5.2,DRX-7.1/R1.1,DRC-R1.1
6
E
D
C
B
A