Table of Contents
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1
A
Pin Function
No.
Pin Name
1
AIP1A
2
AIP1B
3
PLL_AGND
4
PLL_AVDD
5
XTAL1
6
XTAL2
7
AGND
8
RESETB
B
9
PCLK/SCLK
10
IO_DVDD
11
YOUT(7)/I2CSEL
12
YOUT6
13
YOUT5
14
YOUT4
15
YOUT3
16
YOUT2
17
YOUT1
18
YOUT0
C
19
DGND
20
DVDD
21
SCL
22
SDA
23
FID/GLCO
24
VSYNC/PALI
25
HSYNC
26
AVID
INTREQ/GPCL
D
27
/VBLK
28
PDN
29
REFP
30
REFM
31
CH_AGND
32
CH_AVDD
E
F
68
1
2
I/O
I
Analog input
I
Analog input
I
PLL ground Connect to analog ground.
I
PLL power supply (1.8V)
I
External clock reference
O
External clock reference
I
Substrate Connect to analog ground.
I
Active-low reset
O
System clock at either 1x or 2x the frequency of the pixel clock
I
Digital power supply (3.3V)
I2CSEL: Determines address for I
I/O
YOUT7: MSB of output decoded ITU-R BT.656 output/YCbCr 4:2:2 output
I/O
Output decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync
I/O
Output decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync
I/O
Output decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync
I/O
Output decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync
I/O
Output decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync
I/O
Output decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync
I/O
Output decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync
I
Digital ground
I
Digital power supply (1.8V)
I/O
I
2
C serial clock (open drain)
2
I/O
I
C serial data (open drain)
FID: Odd/even field indicator or vertical lock indicator
O
GLCO: This serial output carries color PLL information
VSYNC: Vertical synchronization signal
O
PALI: PAL line indicator or horizontal lock indicator
O
Horizontal synchronization signal
O
Active video indicator
INTREQ: Interrupt request output
I/O
GPCL: General-purpose control logic
I
Power-down terminal (active low)
I
A/D reference supply
I
A/D reference ground
I
Analog ground
I
Analog power supply (1.8V)
2
3
Pin Function
2
C (sampled during reset)
PDP-R06G
3
4
4
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