Marantz SR5014 Service Manual page 61

W9812G6KH-5 (DIGITAL : U1023)
Pin description
PIN NUMBER PIN NAME FUNCTION
23 26, 22,
A0 A11 Address
29 35
20, 21 BS0, BS1 Bank Select
2, 4, 5, 7, 8,
10, 11, 13, 42, Data Input/
DQ0
44, 45, 47, 48, DQ15 Output
50, 51, 53
19 Chip Select
Row Address
18
Strobe
Column Address
17
Strobe
16 WE Write Enable
LDQM, Input/Output
39, 15
UDQM Mask
38 CLK Clock Inputs
37 CKE Clock Enable
1, 14, 27 V Power (+3.3V)
DD
28, 41, 54 V Ground
SS
Power (+3.3V)
3, 9, 43, 49 V
DDQ
for I/O Buffer
Ground for I/O
6, 12, 46, 52 V
SSQ
Buffer
36, 40 NC No Connection No connection.
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0 A11. Column address: A0 A8.
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock, , and WE define the
operation to be executed.
Referred to
Referred to
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising edge
of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend mode
or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Separated power from V , used for output buffers to
DD
improve noise.
Separated ground from V , used for output buffers to
SS
improve noise.
Block diagram
CLK
CLOCK
BUFFER
CKE
CS
CONTROL
SIGNAL
GENERATOR
RAS
COMMAND
DECODER
CAS
WE
R
O
W
D
E
A10 C
O
D
E
MODE R
REGISTER
A0
ADDRESS
BUFFER
A9
A11
BS0
BS1
REFRESH
COLUMN
COUNTER
COUNTER
R
O
W
D
E
C
O
D
E
R
61
COLUMN DECODER
COLUMN DECODER
R
O
W
CELL ARRAY D
CELL ARRAY
E
BANK #0 C
BANK #1
O
D
E
R
SENSE AMPLIFIER
SENSE AMPLIFIER
DMn
DATA CONTROL DQ
CIRCUIT BUFFER
COLUMN DECODER
COLUMN DECODER
R
O
W
CELL ARRAY CELL ARRAY
D
E
BANK #3
BANK #2
C
O
D
E
R
SENSE AMPLIFIER SENSE AMPLIFIER
DQ0
DQ15
UDQM
LDQM