Table of Contents
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CY8C4045AZI-S413 (IC8001)
Block Diagram
CPU Subsystem
PSoC 4000S
Architecture
SWD/ TC
Cortex
M0+
32- bit
48 MHz
FAST MUL
AHB- Lite
NVIC, IRQMUX
System Resources
Lite
Peripherals
Power
Sleep Control
WIC
PCLK
POR
REF
PWRSYS
Clock
Clock Control
WDT
ILO
IMO
Reset
Reset Control
XRES
Test
TestMode Entry
Digital DFT
Analog DFT
Power Modes
Active/ Sleep
DeepSleep
I/O Subsystem
SPCIF
FLASH
SRAM
ROM
32 KB
4 KB
8 KB
Read Accelerator
SRAM Controller
ROM Controller
System Interconnect ( Single Layer AHB)
Peripheral Interconnect (MMIO)
High Speed I/ O Matrix & 2 x Programmable I/O
36x GPIOs, LCD
37
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