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Lattice Semiconductor HDR-60 User Manual

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Summary of Contents for Lattice Semiconductor HDR-60

  • Page 1 Chipsmall Limited consists of a professional team with an average of over 10 year of expertise in the distribution of electronic components. Based in Hongkong, we have already established firm and mutual-benefit business relationships with customers from,Europe,America and south Asia,supplying obsolete and hard-to-find components to meet their specific needs.
  • Page 2  HDR-60 Base Board – Revision B  User’s Guide April 2014 Revision: EB70_01.2...
  • Page 3 LatticeECP3™-70 FPGA. The HDR-60 Base Board and NanoVesta Head Board have been designed to work together as part of the HDR-60 Video Camera Development Kit. Connections are available on the HDR-60 Base Board for the A-1000 HDRI sensor from Aptina, scalable to future sensors from Aptina, and adaptable to sensors from other manufacturers by redesigning the add-on NanoVesta Head Board.

  • Page 4: General Description

    • ispVM™ System programming support General Description The heart of the HDR-60 Base Board is the LatticeECP3 FPGA. The devices and connectors attached to the LatticeECP3 provide a means to investigate applications developed for High Dynamic Range image signal pro- cessing.

  • Page 5: Electrical, Mechanical, And Environmental Specifications

    HDR-60 Base Board – Revision B Initial Setup and Handling The following is recommended reading prior to removing the evaluation board from the static shielding bag and may or may not apply to your particular use of the board. CAUTION: The devices on the board can be damaged by improper handling.

  • Page 6: Functional Description

    HDR-60 Base Board – Revision B Functional Description Figure 2. HDR-60 Base Board, Top View HDMI RJ45 & 2x USB Head Board Head Board Aptina ISSI LatticeECP3-70 Broadcom FTDI Discera MEMs 12 V BNC (Not present Connector Connector Headboard DDR2...
  • Page 7 HDR-60 Base Board – Revision B reference. By doing this, the regulator output voltage remains at a constant voltage value independent of the load driven. Each regulator output voltage follows this equation: = (1 + resistor ratio) x (regulator internal reference voltage) See the LT3503 and LT3508 device data sheets for additional details about these devices.
  • Page 8 VDDIO Figure 3 shows the HDR-60 Base Board default jumpers settings for VDDIO set to 2.5 V. By installing a jumper on J4 in the upper position, the VDDIO will change to 1.8 V and on the lower position, the VDDIO will change to 3.3 V.
  • Page 9 SLVS_6P — SLVS_6N — SLVS_7P — SLVS_7N — SLVS_CP — SLVS_CN — — — HISPI_RESETN — Note 1 RESERVED_1 — Note 1 HISPI_SDATA — — HISPI_SCLK — — VDDIO_rH 1. Routed on the HDR-60 Base Board as a differential pair.
  • Page 10 Connectors J7 and J8 make up the Aptina Head Board connector. They are described below. Note that jumpers J5 and J6 may be required to be in the 2 and 3 positions if using Aptina DevWare software. Contact Aptina for details on running DevWare on the HDR-60 Base Board. Dual Row Connector (J7) The LatticeECP3 (U2) bank 0 interfaces to the Aptina dual row connector (J7) as shown in Table 8.
  • Page 11 HDR-60 Base Board – Revision B Table 8. LatticeECP3 (U2) Interface to Aptina Dual Row Connector (J7) (Continued) J7 Pin LatticeECP3 I/O BGA Ball sysIO Bank Signal HEAD_DOUT5 HEAD_DOUT6 HEAD_DOUT7 HEAD_DOUT8 HEAD_DOUT9 HEAD_LINE_VALID HEAD_SP5 HEAD_SP7 HEAD_SENSOR_RESETN HEAD_FRAME_VALID HEAD_SHIP_CLK HEAD_SP6 HEAD_PIXCLK...
  • Page 12 Base Board. Each USB-A to USB-A cable is 6’ (1.83 m) in length. As both ends of the USB cables are the same, either end can plug into a PC’s USB port, while the other end connects to the HDR-60 Base Board J12 upper USB port.
  • Page 13 LEDs There are three LEDs on the HDR-60 Base Board that are used to show the programming state of the LatticeECP3. See Table 11 for information on the programming state LEDs. Table 11. Programming LEDs...
  • Page 14 HDR-60 Base Board – Revision B Table 12. LatticeECP3 Interface to DDR2 SDRAM (Continued) Signal Name LatticeECP3 I/O Pin (U2) sysIO Bank DDR2 SDRAM Pin (U1) DDR2_A0 AB19 DDR2_A1 DDR2_A2 AA21 DDR2_A3 DDR2_A4 AB17 DDR2_A5 DDR2_A6 DDR2_A7 DDR2_A8 AB18 DDR2_A9...
  • Page 15 HDR-60 Base Board – Revision B provide a legacy Ethernet coaxial link using the BNC connector (J11) by removing three resistors off the HDR-60 Base Board and then add back on three resistors as shown in Table 14. However, Ethernet-over-BNC is an unsup- ported feature on this board.
  • Page 16 SRAM by cycling the power to the evaluation board. The Lattice HDR-60 Base Board provides support for two types of download cable connections: a standard USB-A to USB-A cable at J12, or a Lattice ispDOWNLOAD cable (USB type or parallel port type with flywire connections) at J3 as described in Appendix C.
  • Page 17 HDR-60 Base Board – Revision B Figure 4. Setting the ispVM Custom Scan Option 5. Select Options > Cable and I/O Port Setup. For the Cable Type, select USB2, then click OK. 6. Push the Scan button. You should now see the LFE3-95/70 device listed in the New Scan Configuration Setup window.
  • Page 18 HDR-60 Base Board – Revision B Figure 7. Bitstream Ready to Download into LatticeECP3 SRAM 10. Click Project >Download or the green Go button to download the bitstream into the LatticeECP3 device (U2). A small window will appear as shown in Figure 8. It will take about 12 seconds to download the bitstream for a PC with USB 2.0 ports.
  • Page 19 HDR-60 Base Board – Revision B 2. Connect the USB-A to USB-A cable from your PC’s USB connector to the upper USB port on J12 on the HDR- 60 Base Board. 3. Connect the 12 V wall power adaptor cable to J10 and check to see that the wall power adapter is plugged in to a 120 VAC source.
  • Page 20 HDR-60 Base Board – Revision B Figure 11. SPI Flash Device Setup Complete Figure 12. Bitstream Ready to Download into SPI Flash 11. Click Project > Download or the green Go button to download the bitstream into the SPI Flash device (U9), the bitstream download progress indictor will pop up as shown in Figure 13.
  • Page 21 Figure 14. SPI Flash Download Operation Successful 12. Unpower the HDR-60 Base Board for a few seconds then power it back up. The design will load into the LatticeECP3 (U2) from the external SPI Flash (U9) in two seconds, and the “DONE” LED (LED3) will light up.

  • Page 22: Ordering Information

    Updated Technical Support Assistance information. © 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of...
  • Page 23 HDR-60 Base Board Block Diagram Rev B, 484 ball, -70 Aptina Nanovesta Head Board Head Board (Sheet 8) (Sheet 8) Built In USB 2.0 Download (top view) Programming Bank0 Bank1 (Sheet 6) (Sheet 8) (Sheet 8) 1000Base-T Bank8 PHY/RJ45 (Sheet 6)
  • Page 24 Voltage Regulators Voltage Regulators Voltage Regulators Size Size Size Project Project Project HDR-60 Base Board Schematic HDR-60 Base Board Schematic HDR-60 Base Board Schematic Date: Date: Date: Wednesday, September 21, 2011 Wednesday, September 21, 2011 Wednesday, September 21, 2011 Sheet...
  • Page 25 Core Power ^ DQS Density shown as -70 Size Size Size Project Project Project HDR-60 Base Board Schematic HDR-60 Base Board Schematic HDR-60 Base Board Schematic Date: Date: Date: Wednesday, September 21, 2011 Wednesday, September 21, 2011 Wednesday, September 21, 2011...
  • Page 26 Size Size Size Project Project Project DSC1001-CE-25-000 Ferrites are all 0.45 ohm, 200ma, 0603 HDR-60 Base Board Schematic HDR-60 Base Board Schematic HDR-60 Base Board Schematic Date: Date: Date: Wednesday, September 21, 2011 Wednesday, September 21, 2011 Wednesday, September 21, 2011...