Schematic Diagram - Main Board (1/3) - Sony SS-CEP50 Service Manual

HCD-EP50
Ver 1.1
6-7. SCHEMATIC DIAGRAM – MAIN Board (1/3) – •
MAIN BOARD
(1/3)
TP
(AM VT)
CN12
AM ANT
CN13
(EXCEPT AEP, UK, CH)
FM ANT
75Ω
COAXIAL
(AEP, UK, CH)
1SS133T
R239
3.3M
1/2W
1SS133T
0.001
(EXCEPT AEP, UK, CH)
RF INPUT i
TP
GND i
(FM VT)
0.047
GND i
11.3
12.5 (0)
G
GND i
12 (0.1)
INCLUDED IN
VT i
MAIN BOARD
VCC i
(Page 19)
Q4, 10
B+ SWITCH
IF OUTPUT i
12.2 (0.1)
0.1 (0.7)
OSCO i
1
CLOCK i
MAIN BOARD i
DA_IN
(2/3)
(Page 21)
RR-CH i
RL-CH i
2
MAIN BOARD
(2/3) TR-CH i
(Page 21)
TL-CH i
CN3
9P
* CD DA
BLOCK
CLK
* SUPPLIED AS THE
ASSEMBLED BLOCK
NC
RESET
0.001
0.001
•
See page 28 for Waveform. See page 28 for IC Block Diagrams.
T8
AM FREQUENCY
COVERRAGE
T6, TC1
0.047
AM TRACKING
AM RF
0.001
U1
FM/AM IF AMP,
FRONT-END AM RF AMP/MIX/OSC,
FM/AM DET, MPX
(EXCEPT AEP, UK, CH)
8.6 (0)
3.4 (0)
0.001 FM IF AMP
2.6 (0)
0.047
0.01
(AEP, UK, CH)
0.0056
50V
0.1
0.1 0.1
0.1
0.1
0.1
50V
1SS133T
0.1
U6
INPUT SELECT SWITCH,
ELECTRICAL VOLUME
IC B/D
Q3
FM/AM BAND
SELECT SWITCH
50V
L. P. F.
L. P. F.
0.0047
0.0047
50V
0.047
50V
50V
6.7 (0.1)
0.1
(0.7)
3.6
U1
LA1837
IC B/D
0.047
AM IF
50V
50V
5
8.1
50V
VCC
4.5
4.5
50V
4.4
4.4
GND
0.033
50V
20 20
Q17
STEREO/MONO
SWITCHING
50V (AEP, UK, CH)
0.1
0.001
2.8
1.6
0.9
BUFFER
0.001
6.7
0
0 0
IFIN
IO1
0.001
IO2
BO4
0.001
0 (2.3)
AMIN
BO3
2.3 (0)
FMIN
BO2
4.9 0.1 (4)
VDD BO1
0.9 4.9
PD
DO
0.9 4.9
AIN CL
1.3 0
AOUT DI
0
VSS CE
2.4 2.3
U2
XOUT XIN
1
0.1 FM/AM PLL
IC B/D
Q13, 16
MEGA BASS CONTROL SWITCH
0
0
0
0
U3
LINE AMP
0.022
4.5
50V
0 0
0 0
4.4
Q6, 7
MUTING
50V
4.9 4.9
4.1
0.1
0.7
Q1, 11
B+ SWITCH
i TU-EN
3
i TIMER
MAIN BOARD
i STR (2/3)
(Page 21)
CN4
3P
RDS_DA
A
DSIPLAY
BOARD
(Page 25)
CN11
7P
B
DSIPLAY
BOARD
(Page
25)
4
i POWER-FAIL
MAIN BOARD
i POWER-LINE
(3/3)
(Page 22)
50V
CN5
11P
C
DSIPLAY
BOARD
RESET (Page
DA
25)
CLK
(Page 21)
5
i REC. LED+
i BEAT MAIN BOARD
(2/3)
i R-CH
6
i MUTE-LINE
MAIN BOARD
i L-CH
(3/3)
(Page 22)