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M93C46-WDW6T (ST MICROELECTRONICS)
SERIAL MICROWIRE BUS EEPROM 1Kbit
– TOP VIEW –
M93C06/46/56/66 - W
Warning: DU = Don't Use
Table 1. Signal Names
Figure 1. Logic Diagram
MAX1908ETI+TG069 (MAXIM)
LOW-COST MULTICHEMISTRY BATTERY CHARGER
TOP VIEW
DCIN
1
LDO
2
CLS
3
REF
4
CCS
5
CCI
6
CCV
7
ELECTRICAL CHARACTERISTICS
(V
= V
= V
= 18V, V
= V
= V
DCIN
CSSP
CSSN
BATT
CSIP
REF, V
- V
= 4.5V, ACIN = GND = PGND = 0, C
BST
LX
per Figure 1a; T
= 0°C to +85°C, unless otherwise noted. Typical values are at T
A
PARAMETER
SYMBOL
CHARGE VOLTAGE REGULATION
V
Battery Regulation Voltage
V
Accuracy
V
VCTL Default Threshold
V
REFIN Range
(Note 1)
REFIN Undervoltage Lockout
V
CHARGE CURRENT REGULATION
CSIP to CSIN Full-Scale Current-
V
Sense Voltage
V
Charging Current Accuracy
V
V
ICTL Default Threshold
V
BATT/CSIP/CSIN Input Voltage
Range
V
CSIP/CSIN Input Current
V
Cycle-by-Cycle Maximum Current
I
RS2 = 0.015Ω
MAX
Limit
ICTL Power-Down Mode
V
Threshold Voltage
V
ICTL, VCTL Input Bias Current
V
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= 18V, V
= V
= V
DCIN
CSSP
CSSN
BATT
CSIP
REF, V
- V
= 4.5V, ACIN = GND = PGND = 0, C
BST
LX
per Figure 1a; T
= 0°C to +85°C, unless otherwise noted. Typical values are at T
A
PARAMETER
SYMBOL
V
REFIN Input Bias Current
V
ICHG Transconductance
G
V
ICHG
V
ICHG Accuracy
V
V
ICHG Output Current
V
ICHG Output Voltage
V
INPUT CURRENT REGULATION
CSSP-to-CSSN Full-Scale
Current-Sense Voltage
V
Input Current-Limit Accuracy
V
CSSP, CSSN Input Voltage
Range
V
CSSP, CSSN Input Current
V
CLS Input Range
CLS Input Bias Current
V
IINP Transconductance
G
V
IINP
V
IINP Accuracy
V
IINP Output Current
V
IINP Output Voltage
V
SUPPLY AND LDO REGULATOR
DCIN Input Voltage Range
V
DCIN
V
DCIN Undervoltage Lockout Trip
Point
V
DCIN Quiescent Current
I
8.0V < V
DCIN
V
BATT Input Current
I
BATT
V
LDO Output Voltage
8V < V
LDO Load Regulation
0 < I
LDO Undervoltage Lockout Trip
V
Point
REFERENCE
REF Output Voltage
0 < I
VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/
S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F
1-25
21
DLO
20
PGND
19
CSIP
MAX1908
18
CSIN
17
CELLS
16
BATT
15
VCTL
THIN QFN
= 12V, V
= 3V, V
= V
= 0.75 x V
, CELLS = float, CLS =
CSIN
REFIN
VCTL
ICTL
REFIN
= 1µF, LDO = DLOV, C
= 1µF; CCI, CCS, and CCV are compensated
LDO
REF
= +25°C.)
A
CONDITIONS
MIN
TYP
= V
(2, 3, or 4 cells)
-0.5
VCTL
REFIN
= V
/20 (2, 3, or 4 cells)
-0.5
VCTL
REFIN
= V
(2, 3, or 4 cells)
-0.5
VCTL
LDO
rising
4.0
4.1
VCTL
2.5
falling
1.20
REFIN
= V
71.25
75
ICTL
REFIN
= V
-6
ICTL
REFIN
= V
x 0.6
-5
ICTL
REFIN
= V
-6
ICTL
LDO
rising
4.0
4.1
ICTL
0
= 0 or SHDN = 0
= 0 or V
DCIN
ICTL
= V
= 12V
400
CSIP
CSIN
6.0
6.8
REFIN /
REFIN /
rising
ICTL
100
55
= V
= 0 or 3V
-1
VCTL
ICTL
= 0, V
= V
= V
= 5V
-1
DCIN
VCTL
ICTL
REFIN
= 12V, V
= 3V, V
= V
= 0.75 x V
, CELLS = float, CLS =
CSIN
REFIN
VCTL
ICTL
REFIN
= 1µF, LDO = DLOV, C
= 1µF; CCI, CCS, and CCV are compensated
LDO
REF
= +25°C.)
A
CONDITIONS
MIN
TYP
= 5V, V
= 3V
-1
DCIN
REFIN
= 5V
-1
REFIN
- V
= 45mV
2.7
3
CSIP
CSIN
- V
= 75mV
-6
CSIP
CSIN
- V
= 45mV
-5
CSIP
CSIN
- V
= 5mV
-40
CSIP
CSIN
- V
= 150mV, V
= 0
350
CSIP
CSIN
ICHG
- V
= 150mV, ICHG = float
3.5
CSIP
CSIN
71.25
75
= V
-4
CLS
REF
= V
/ 2
-7.5
CLS
REF
8
= 0
0.1
DCIN
= V
= V
> 8V
350
CSSP
CSSN
DCIN
1.6
= 2V
-1
CLS
- V
= 75mV
2.7
3
CSSP
CSSN
- V
= 75mV
-5
CSSP
CSSN
- V
= 37.5mV
-7.5
CSSP
CSSN
- V
= 150mV, V
= 0
350
CSSP
CSSN
IINP
- V
= 150mV,V
= float
3.5
CSSP
CSSN
IINP
8
falling
7
7.4
DCIN
rising
7.5
DCIN
< 28V
3.2
DCIN
= 19V, V
= 0
BATT
DCIN
= 2V to 19V, V
= 19.3V
200
BATT
DCIN
< 28V, no load
5.25
5.4
DCIN
< 10mA
34
LDO
= 8V
3.20
4
DCIN
< 500µA
4.072
4.096
REF
Confidential
(J/AM/AO)
IC
MAX
UNITS
+0.5
+0.5
%
+0.5
4.2
V
3.6
V
1.92
V
78.75
mV
+6
+5
%
+6
4.2
V
19
V
1
µA
650
7.5
A
REFIN /
V
33
+1
µA
+1
MAX
UNITS
+1
µA
+1
3.3
µA/mV
+6
+5
%
+40
µA
V
78.75
mV
+4
%
+7.5
28
V
1
µA
600
REF
V
+1
µA
3.3
µA/mV
+5
%
+7.5
µA
V
28
V
V
7.85
6
mA
1
µA
500
5.55
V
100
mV
5.15
V
4.120
V
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