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TS-2200 User's Manual
6 Digital I/O
6.1 DIO1 Header
The DIO1 port provides +5V, GND, and 12 digital I/O lines that may
be used to interface the TS-2200 with a wide range of external
devices. Additional digital I/O is available on the DIO2 header. These
signals are connected directly to the 386EX and several have
multiple functions. For example, DIO pins 6, 11, 12, and 13 are by
default IRQ7, IRQ3, IRQ4, and IRQ5 respectively. By setting configu-
ration registers in the 386EX, these pins can be individually changed
to general purpose I/O (GPIO) as high-impedance inputs, open-drain
outputs, or complementary outputs. Note that these same signals are also connected directly to the
PC/104 bus; if a pin is configured as GPIO, then the associated IRQ will not be available for PC/104
expansion cards.
DIO pins 7-10 can be configured as a synchronous serial port supporting baud rates to 6.25Mbaud.
These pins are COM2 handshake lines by default that can be also used as GPIO.
DIO pins 3, 4, 5, and 14 are always GPIO – they do not have secondary functions.
All digital outputs can source or sink up to 8mA. All digital inputs have standard TTL level thresholds.
For further information on configuration and use of these pins, See Appendix G.
6.2 DIO2 Header
Up to 13 additional DIO lines are available on the DIO2 Header. Pins
1,3,5,and 7 are digital inputs with 10K Ohm pull-up resistors that can
be read at I/O location 77h bits 1-4. Pin 4 is a Digital output that
drives the TS-2200 LED. Pins 6,8,13,and 14 are i386EX
programmable I/O lines. Pin 10 is a fixed input that can be read
(inverted polarity) at the COM2 Status Reg. (I/O location 2FEh bit 7).
Pin 12 is the signal that enables the RS-485 Transmit driver. If the
RS-485 option is not installed, this pin can be read as input at I/O
location 77h bit 0. Pins 9 and 11 are open-drain active-low outputs that drive the Ethernet Link and
LAN LEDs. The default configuration is for these to be driven by the Ethernet controller to indicate
network presence and activity. These can be reprogrammed to be general-purpose outputs. For more
information regarding these 2 lines, please consult the Cirrus Logic CS8900A Users Guide in
Appendix H.
Note – DIO2 pin 14 (P1.3) is also shared with user jumper JP3. If user jumper JP3 is being used, then
DIO2 pin 14 should be left not connected.
For further information on configuration and use of these pins, See Appendix G.
DTR2 / SRXCLK
DSR2 / STXCLK
Figure 3 – DIO2 Header Pinout
10
Technologic Systems
P3.2
IRQ5 / P3.3
14 13
IRQ4 / P3.0
12 11
IRQ3 / P3.1
10 9
RI2 / SRXD
8
7
RTS2 / STXD
IRQ7 / P3.5
6
5
P1.0
P1.5
P3.6
4
3
GND
2
1
5V
Figure 2 – DIO1 Header Pinout
P1.3
IRQ6 / P3.4
14 13
TX485EN
LinkLED#
12 11
DCD2
10 9
RxLED#
RTS1 / P1.1
8
7
IN1@77
P1.2
6
5
IN2@77
LED-ON
4
3
IN3@77
GND
IN4@77
2
1
11/06/2000
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