NEC IE-178098-NS-EM1 User Manual page 37

CHAPTER 4
(2) Signals input from the target system via a gate
Since the following signals are input via a gate, their timing shows a delay compared to that of the µ PD178078,
178098 Subseries, and µ PD178F098. Their AC characteristics and DC characteristics are therefore different
from the µ PD178078, 178098 Subseries, and µ PD178F098, making it necessary to observe a stricter timing
design than in the case of the the µ PD178078, 178098 Subseries, and µ PD178F098.
• RESET signal
• Signals related to clock input
In all the signals input from the target system, the RESET signal, and signals related to clock input are input to
the evaluation chip via a logic IC. The DC characteristics are therefore different from the µ PD178078, 178098
Subseries, and µ PD178F098. The AC characteristics are also different because of the delayed signal timing
caused by the gate.
Probe side
RESET
X1
(3) Signals related to PLL
• AMIFC
• FMIFC
• VCOH
• VCOL
• REGOSC
• REGCPU
• V
PLL
DD
• GNDPLL
DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS
Figure 4-2. Equivalent Circuit 2 of Emulator
HC4066
LV
CC
1 MΩ HSK120
User's Manual U14013EJ2V0UM00
IE-178098-NS-EM1 side
LV
CC
4.7 kΩ
HD151015
HD151015
RESET
X1
37