Figure 2-2. Hss-Motherboardevm Sample Daughter Card Schematic - Texas Instruments HSS-MOTHERBOARDEVM User Manual

HSS-MOTHERBOARDEVM Schematic
U1_S
Vbb_1_A Vout1_1_S S _A
25 6
VBB VOUT1
7 Vout1_1_A
VOUT1
DIA_EN_1_A
24 8
DIA_EN VOUT1
9
VOUT1
S EL1_1_A 22 10
S EL1 VOUT1
11
VOUT1
S EL2_1_A
23 12
S EL2 VOUT1
EN1_1_A
4
EN1
Vout2_1_A
13
VOUT2
EN2_1_A 21 14
EN2 VOUT2
15
VOUT2
LATCH_1_A
3 16
LATCH VOUT2
17
VOUT2
18
VOUT2
ILIM1_1_A Vout2_1_S S _A
5 19
ILIM1 VOUT2
ILIM2_1_A
20
ILIM2
GND_1_A
1
GND
S NS _1_A 2
S NS
TP S 2HB08DQP WP RQ1
Vbb_1_A ILIM1_1_A ILIM2_1_A
C2_S R3_S R4_S
50V 10.0k 10.0k
0.1uF
GND_1_A Vbb_1_A Vbb_1_A
J1_S J2_S
Vout1_1_A Vout2_1_A
12 1
11 2
10 3
Vout1_1_S S _A Vout2_1_S S _A
9 4
8 ILIM1_1_A ILIM2_1_A 5
EN1_1_A EN2_1_A
7 6
LATCH_1_A S EL1_1_A
6 7
5 S NS _1_A S EL2_1_A 8
GND_1_A DIA_EN_1_A
4 9
3 10
2 11
Vbb_1_A Vbb_1_A
1 12
Vout1_1_A Vout2_1_A
J10_S
6 High Side Switch Motherboard Evaluation Module
U2_S
Vbb_1_B Vout1_1_S S _B
25 6
VBB VOUT1
7 Vout1_1_B
VOUT1
DIA_EN_1_B
24 8
DIA_EN VOUT1
9
VOUT1
S EL1_1_B 22 10
S EL1 VOUT1
11
VOUT1
S EL2_1_B
23 12
S EL2 VOUT1
EN1_1_B
4
EN1
Vout2_1_B
13
VOUT2
EN2_1_B 21 14
EN2 VOUT2
15
VOUT2
LATCH_1_B
3 16
LATCH VOUT2
17
VOUT2
18
VOUT2
ILIM1_1_B Vout2_1_S S _B
5 19
ILIM1 VOUT2
ILIM2_1_B
20
ILIM2
GND_1_B
1
GND
S NS _1_B 2
S NS
TP S 2HB08BQP WP RQ1
Vbb_1_B ILIM1_1_B ILIM2_1_B
C3_S R5_S R6_S
50V 10.0k 10.0k
0.1uF
GND_1_B Vbb_1_B Vbb_1_B
J3_S J4_S
Vout1_1_B Vout2_1_B
12 1
11 2
10 3
Vout1_1_S S _B Vout2_1_S S _B
9 4
8 ILIM1_1_B ILIM2_1_B 5
EN1_1_B EN2_1_B
7 6
LATCH_1_B S EL1_1_B
6 7
5 S NS _1_B S EL2_1_B 8
GND_1_B DIA_EN_1_B
4 9
3 10
2 11
Vbb_1_B Vbb_1_B
1 12
Vout1_1_B Vout2_1_B
J11_S
Vbb_3_C
C5_S
50V
0.1uF
GND_3_C
12
11
10
9 Vout1_3_S S _C
ILIM1_3_C
8
EN1_3_C
7
6 LATCH_3_C
S NS _3_C
5
GND_3_C
4
3
2
1
J13_S
Vout1_3_C

Figure 2-2. HSS-MOTHERBOARDEVM Sample Daughter Card Schematic

Copyright © 2020 Texas Instruments Incorporated
U3_S
Vbb_3_B
17
VBB VOUT1
VOUT1
EN1_3_B
4
EN1 VOUT1
EN2_3_B
13
EN2
VOUT2
LATCH_3_B
3
LATCH VOUT2
S EL1_3_B
14
S EL1 VOUT2
S EL2_3_B 15
S EL2
DIA_EN_3_B
16
DIA_EN
ILIM1_3_B 5
ILIM1
ILIM2_3_B
12
ILIM2
S NS _3_B 2
S NS GND
TP S 2HB16BQP WP RQ1
Vbb_3_B ILIM1_3_B
C1_S R1_S
50V 10.0k
0.1uF GND_3_B Vbb_3_B
Vout1_3_B Vout2_3_B
12
11
10
Vout1_3_S S _B Vout2_3_S S _B
9
ILIM1_3_B ILIM2_3_B
8
EN1_3_B EN2_3_B
7
6 LATCH_3_B S EL1_3_B
S NS _3_B S EL2_3_B
5
GND_3_B DIA_EN_3_B
4
3
2
Vbb_3_B Vbb_3_B
1
J7_S
Vout1_3_B Vout2_3_B
J9_S
ILIM1_3_C ILIM2_3_C
R9_S R10_S
10.0k 10.0k
Vbb_3_C Vbb_3_C Vbb_3_C
17
EN1_3_C
4
EN2_3_C
13
Vout1_3_C Vout2_3_C 1
LATCH_3_C
2 3
S EL1_3_C
3 14
Vout2_3_S S _C 4 S EL2_3_C 15
ILIM2_3_C
5
EN2_3_C DIA_EN_3_C
6 16
S EL1_3_C 7 ILIM1_3_C 5
S EL2_3_C ILIM2_3_C
8 12
DIA_EN_3_C
9
10 S NS _3_C 2
11
Vbb_3_C Vbb_3_C
12
J14_S
Vout2_3_C
J15_S
Vout1_3_S S _B
6
7 Vout1_3_B
8
9 Vout2_3_B U4_S
10
Vout2_3_S S _B Vbb_2_A
11 17
VBB
EN1_2_A
4
EN1
EN2_2_A
13
EN2
LATCH_2_A
3
LATCH
S EL1_2_A
14
S EL1
1 GND_3_B S EL2_2_A 15
S EL2
DIA_EN_2_A
16
DIA_EN
ILIM1_2_A 5
ILIM1
ILIM2_2_A
12
ILIM2
ILIM2_3_B S NS _2_A 2
S NS
R2_S
TP S 2HB16BQP WP RQ1
10.0k
Vbb_3_B
Vbb_2_A
C4_S
50V
1
0.1uF GND_2_A
2
3
4
5
J5_S
6
7 12 Vout1_2_A
8 11
9 10
10 9 Vout1_2_S S _A
ILIM1_2_A
11 8
EN1_2_A
12 7
6 LATCH_2_A
J8_S S NS _2_A
5
GND_2_A
4
3
2
Vbb_2_A
1
Vout1_2_A
U5_S
Vout1_3_S S _C
6
VBB VOUT1
7 Vout1_3_C
VOUT1
8
EN1 VOUT1
EN2
9 Vout2_3_C
VOUT2
10
LATCH VOUT2
Vout2_3_S S _C
11
S EL1 VOUT2
S EL2
DIA_EN
ILIM1
ILIM2
1 GND_3_C
S NS GND
TP S 2HB16BQP WP RQ1
SLVUBD4B – JANUARY 2018 – REVISED OCTOBER 2020
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Vout1_2_S S _A
6
VOUT1
7 Vout1_2_A
VOUT1
8
VOUT1
9 Vout2_2_A
VOUT2
10
VOUT2
Vout2_2_S S _A
11
VOUT2
1 GND_2_A
GND
ILIM1_2_A ILIM2_2_A
R7_S R8_S
10.0k 10.0k
Vbb_2_A Vbb_2_A
J6_S
Vout2_2_A 1
2
3
Vout2_2_S S _A 4
ILIM2_2_A
5
EN2_2_A
6
S EL1_2_A 7
S EL2_2_A
8
DIA_EN_2_A
9
10
11
Vbb_2_A
12
Vout2_2_A
J12_S