Compaq Deskpro EP 6233 Technical Reference Manual page 46

Chapter 3 Processor/Memory Subsystem
3.3.1 PENTIUM II PROCESSOR
The Intel Pentium II processor is packaged in a Single Edge Connector (SEC) cartridge that
contains the microprocessor and 512-KB secondary (L2) cache (Figure 3-6). The cartridge
installs into a Slot 1-type connector on the system board, allowing easy replacing/upgrading of
the processor/cache memory complex.
Figure 3–6. 350-/400-MHz Pentium II Processor Internal Architecture
The Pentium II processor is software-compatible with earlier generation x86 microprocessors.
The microprocessor includes a dual-ALU MMX-supporting CPU, branch prediction logic, dual-
pipeline math coprocessor, and a 32-KB cache that is split into two 16-KB 4-way, set-associative
caches for handling code and data separately. Processing occurs at 350- or 400-MHz depending
on version.
The Pentium II processor includes 512 kilobytes of SRAM for the L2 cache. Accesses with the
L2 cache occur at half the processor core speed. The front side (Host) bus of the processor
operates at 100 MHz.
3.3.1.1 MMX Technology
The CPU of the Pentium II supports 57 additional instructions for accelerating multimedia and
communications applications. Such applications often involve compute-intensive loops that can
take up as much as 90 percent of CPU execution time. The MMX logic, using a parallel
processing technique called Single Instruction-Multiple Data (SIMD), processes 64 bits of data at
a time. The MMX instructions are designed to take advantage of the dual-pipeline CPU as well
as help the programmer in avoiding branches in code. Specific applications that benefit from
MMX technology include 2D/3D graphics, audio, speech recognition, video codecs, and data
compression.
NOTE: MMX operations utilize a portion of the floating point registers of the
integrated math coprocessor. Programmers should avoid the mixing of MMX and
floating point code, which would reduce performance.
3-10 Compaq Deskpro EP Series of Personal Computers
Pentium II Processor
Dual-ALU
32-KB
CPU w/MMX
L1 Cache
Branch Dual Pipeline
Prediction Math Coproc.
First Edition - April 1998
512-KB
L2
Cache