Download Print this page

Waveshare 10451 User Manual page 7

1.3inch oled

Advertisement

share awesome hardware
1.3inch OLED User Manual
address is set by connecting the input SA0 to either logic 0(VSS) or 1 (VDD1). The I2C-bus protocol is
illustrated in Figure 6: I2C Protocol. The sequence is initiated with a START condition (S) from the
I2C-bus master that is followed by the slave address. All slaves with the corresponding address
acknowledge in parallel, all the others will ignore the I2C-bus transfer. After acknowledgement, one
or more command words follow which define the status of the addressed slaves. A command word
consists of a control byte, which defines Co and D/C (note1), plus a data byte (see Figure 6: I2C
Protocol). The last control byte is tagged with a cleared most significant bit, the continuation bit Co.
After a control byte with a cleared Co-bit, only data bytes will follow. The state of the D/C -bit defines
whether the data-byte is interpreted as a command or as RAM-data. The control and data bytes are
also acknowledged by all addressed slaves on the bus. After the last control byte, depending on the
D/C bit setting, either a series of display data bytes or command data bytes may follow. If the D/C bit
was set to '1', these display bytes are stored in the display RAM at the address specified by the data
pointer. The data pointer is automatically updated and the data is directed to the intended SH1106
device. If the D/C bit of the last control byte was set to '0', these command bytes will be decoded and
the setting of the device will be changed according to the received commands. The acknowledgement
after each byte is made only by the addressed slave. At the end of the transmission the I2C-bus
master issues a stop condition (P). If the R/W bit is set to one in the slave-address, the chip will output
data immediately after the slave-address according to the D/C bit, which was sent during the last
write access. If no acknowledge is generated by the master after a byte, the driver stops transferring
data to the master.
Figure 6: I2C Protocol
7
th
Rev 2.4, May 15
2015

Advertisement

loading