Advertisement
share awesome hardware
1.3inch OLED User Manual
Figure 4: Start and Stop conditions
Acknowledge
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on
the bus by the transmitter during which time the master generates an extra acknowledge related
clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA
line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A
master receiver must signal an end of data to the transmitter by not generating an acknowledge on
the last byte that has been clocked out of the slave. In this event the transmitter must leave the data
line HIGH to enable the master to generate a stop condition.
Figure 5: Acknowledge
Protocol
The SH1106 supports both read and write access. The R/W bit is part of the slave address. Before any
data is transmitted on the I2C-bus, the device that should respond is addressed first. Two 7-bit slave
addresses (0111100 and 0111101) are reserved for the SH1106. The least significant bit of the slave
6
th
Rev 2.4, May 15
2015
Advertisement
