Syntax SV400 Manual page 63

AGP Master 1 WS Write (Disabled)
This implements a single delay when writing to the AGP Bus. By default, two-
wait states are used by the system, providing greater stability.
AGP Master 1 WS Read (Disabled)
This implements a single delay when reading to the AGP Bus. By default, two-
wait states are used by the system, allowing for greater stability.
Press <Esc> to return to the Advanced Chipset Features screen.
CPU & PCI Bus Control
Scroll to this item and press <Enter> to view the following screen:
Phoenix – AwardBIOS CMOS Setup Utility
PCI1 Master 0 WS Write
PCI2 Master 0 WS Write
PCI1 Post Write
PCI2 Post Write
PCI Delay Transaction
↑ ↓ → ← : Move
Enter : Select
F5:Previous Values
PCI 1/2 Master 0 WS Write (Enabled)
When enabled, writes to the PCI bus are executed with zero wait states,
providing faster data transfer.
PCI 1/2 Post Write (Enabled)
When enabled, writes from the CPU to PCU bus are buffered, to compensate
for the speed differences between the CPU and PCI bus. When disabled, the
writes are not buffered and the CPU must wait until the write is complete
before starting another write cycle.
PCI Delay Transaction (Disabled)
The mainboard's chipset has an embedded 32-bit post write buffer to support
delay transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
Press <Esc> to return to the Advanced Chipset Features screen.
Memory Hole (Disabled)
This item is used to reserve memory space for ISA expansion cards that
require it.
System BIOS/Video RAM Cacheable (Disabled)
These items allow the video and system to be cached in memory for faster
CPU & PCI Bridge Control
[Enabled]
[Enabled]
[Enabled]
[Enabled]
[Disabled]
+/-/PU/PD:Value: F10: Save ESC: Exit
F6:Fail-Safe Defaults
36
Item Help
Menu Level
F1:General Help
F7:Optimized Defaults