Advertisement
14.35. D-Board Block Diagram
TO DG5
E+LVDS0
E-LVDS0
E+LVDS1
E-LVDS1
E+LVDS2
E-LVDS2
E+LVDS3
E-LVDS3
E+LVDS4
E-LVDS4
E+LVDSCLK
E-LVDSCLK
LVDS_DET
0+LVDSCLK
0-LVDSCLK
TO DG3
STB 5V
DISPEN
READY
ALARM
IIC_CLK1
IIC_DATA1
PANEL_STB_ON
FAN_CONT(FAN_MAX)
FAN_SOS
ECO_ON
TUNER_SUB_ON
FOR
FACTORY
USE
IIC/INT
IIC_CONT
TO P25
STBY5V
FAN_CONT
FAN_SOS
F_STBY_ON
ECO_ON
PANEL_MAIN_ON
PS_SOS
FOR
FACTORY
USE
DCLK
CONF_DONE
nCONFIG
DATA0
ASDIO
PBUSY
PSLCT
DCDC_ON
XRST
TH-37/42PE55E
D-Board Block Diagram
D
DIGITAL SIGNAL PROCESSOR
FORMAT CONVERTER,
PlASMA AI
SUB-FIELD PROCESSOR
D5
1
2
4
5
6
7
9
10
11
12
14
15
16
17
18
STB 5V
D3
12
DRVMUTE
6
READY
7
ALARM
8
19
P3V_SCL1
20
P3V_SDA1
11
Q9000
FAN_CONT
1
FAN_SOS
3
ECO_ON
4
F_STBY_ON
14
Q9004
Q9001
D4
TXD_PC
TXD
10
RXD_PC
RXD
11
IIC_INT
12
SDA2
SDA2
7
SCL2
6
SCL2
SDA1
SDA1
5
SCL1
SCL1
4
IIC_CONT
2
P12V
D25
+12V
1
P5V
+12V
2
STB5V_M
+5V
7
+5V
9
10
FAN_CONT
3
FAN_SOS
14
F_STBY_ON
13
ECO_ON
15
PANEL_MAIN_ON
17
PS_SOS
16
D6
1
CONF_DONE
DCLK
3
NCONFIG
5
NCE
DATA0
nCE
6
2
DATA
7
nCS
8
1
NCS
9
NCS
PSTB
11
ASDI0
13
15
PDB0
17
PDB1
19
16
18
3.3V
3.3V
4
3.3V
14
R 10bit
G 10bit
B 10bit
LVDS
Low
Voltage
Differential
Signaling
RECEIVER
NCS
NCS
DATA0
DATA0
CONF_DONE
CONF_DONE
NCONFIG
NCONFIG
ASDI0
ASDI0
NCE
NCE
DCLK
DCLK
IC9008
STB5V_M
AVR STB3.3V
STB3.3V
SW
Q9003
2
AVR
4
1
ON/OFF
IC9007
DCLK
6
PROM
5
ADSI
FORMAT CONVERTER/RGB PROCESSOR
I/P
CONVERTER
VD
HD
DCK
R0
G0
B0
VD
HD DCK
R9
G9
B9
PICTURE OUTPUT
IC9500
FPGA/SYNC/OSD/DISCHARGE CONTROL
CONTROL
SCL
SDA
P3V_SCL2
P3V_SDA2
IC9001
EEPROM
SDA
5
SCL
6
P3V_SCL2
Q9008
P3V_SDA2
Q9009
3.3V
D2
D1
Q9702
G2
S2
G1
S1
26
23
27
SW1
BG2
TG2
RUN/SS1
1
IC9300
CTI/TINT
FORMAT
COLOR
CONTRAST
CONVERTER
WB-ADJ
st-r
PCK
OCK
11
CLK8
X1
1
14 CLK5
CLKM_IN
7
CLK1
20
FREE_RUN
X2
10
CLK4
DPCLK5 DPCLK2
DISCHARGE
CONTROL
DATA POWER
FEEDBACK
DATA DRIVER
FPGA CONTROL
SS PULSE
SCAN OUT
SC PULSE
OSD
DRV_RST
R,G,B,HD,VD,CK
NRST
DRVMUTE
P3V_SCL1
Q9012
P3V_SDA1
Q9013
P12V
1.5V
D2
D1
Q9701
G2
S2
G1
S1
24
17
19
16
VIN
SW2
BG2
TG2
IC970
RUN/SS2
DC_DC CO
15
Q9703
101
Advertisement
