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TC94A14FA(IC521):DSP&DAC
1.Terminal layout & block daiagram
48
47
46
49
Clock
50
generator
51
LPF
52
53
54
55
56
57
58
59
60
61
Micro-
62
controller
interface
63
64
1
2
3
2.Pin function
Pin
Symbol
I/O
No
1
BCK
O
Bit clock output pin.32fs,48fs,or 64fs selectable by command.
2
LRCK
O
L/R channel clock output pin."L" for L channel and "H" for R channel. Output polarity
can be inverted by command.
3
AOUT
O
Audio data output pin. MSB-first or LSB-first selectable by command.
4
DOUT
O
Digital data output pin.Outputs up to double-speed playback.
5
IPF
O
Correction flag output pin. When set to "H", AOUT output cannot be corrected by C2
correction processing.
6
V
-
Digital 3.3V power supply voltage pin.
DD3
7
V
-
Digital GND pin.
SS3
8
SBOK
O
Subcode Q data CRCC result output pin. "H" level when result is OK.
9
CLCK
O
Subcode P-W data read I/O pin. I/O polarity selectable by command.
10
DATA
O
Subcode P-W data output pin.
11
SFSY
O
Playback frame sync signal output pin.
12
SBSY
O
Subcode block sync signal output pin. "H" level at S1 when subcode sync is detected.
13
HSO
I/O
General-purpose input / output pins.
14
UHSO
Input port at reset.
15
PV
-
PLL-only 3.3V power supply voltage pin.
DD3
45
44
43
42
41
1-bit
DAC
Address
circuit
16 k
RAM
Audio out
Digital
circuit
output
4
5
6
7
8
Descroption
40
39
38
37
36
PWM
Servo
control
ROM
Digital equalizer
automatic
adjustment circuit
RAM
CLV servo
Synchronous
guarantee
EFM
decoder
Sub code
decoder
9
10
11
12
13
35
34
33
32
31
D/A
30
29
A/D
28
27
26
25
24
Data
slicer
23
22
VCO
21
20
19
PLL
TMAX
18
17
14
15
16
KD-SX787
1-39
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