LG 42GA6400-UD Service Manual page 46

Close to DDR Pin
+1.5V_FRC_DDR
+1.5V_FRC_DDR
R9700
1K
1%
MVREFCA
R9701
1K
1% C9700
0.1uF
+1.5V_FRC_DDR
R9702
1K
1%
MVREFDQ
R9703
1K
1%
C9701
0.1uF
+1.5V_FRC_DDR
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
+1.5V_FRC_DDR
DDR3 1.5V De-Cap
C9702 C9703
0.1uF 22uF
16V 10V
Place Close to DDR Pin
IC9700
H5TQ1G63EFR-PBC
M8 N3 DDR3_A[0]
MVREFCA VREFCA A0
P7 DDR3_A[1]
A1
P3 DDR3_A[2]
A2
H1 N2 DDR3_A[3]
MVREFDQ VREFDQ A3
P8 DDR3_A[4]
A4
P2 DDR3_A[5]
R9704 A5
L8 R8 DDR3_A[6]
ZQ A6
R2 DDR3_A[7]
240
A7
1% T8 DDR3_A[8]
A8
B2 R3 DDR3_A[9]
VDD_1 A9
D9 L7 DDR3_A[10]
VDD_2 A10/AP
G7 R7 DDR3_A[11]
VDD_3 A11
K2 N7 DDR3_A[12]
VDD_4 A12/BC
K8 T3 DDR3_A[13]
VDD_5 NC_7
N1
VDD_6
N9 M7
VDD_7 NC_5
R1
VDD_8
R9 M2
DDR3_BA0
VDD_9 BA0
N8
DDR3_BA1
BA1
M3
BA2 DDR3_BA2
A1
VDDQ_1
A8 J7
VDDQ_2 CK
C1 K7
VDDQ_3 CK
C9 K9
VDDQ_4 CKE
D2
VDDQ_5
E9 L2
VDDQ_6 CS
F1 K1
VDDQ_7 ODT DDR3_ODT
H2 J3
DDR3_RASB
VDDQ_8 RAS
H9 K3
DDR3_CASB
VDDQ_9 CAS
L3
WE DDR3_WEB
J1
NC_1
J9 T2
NC_2 RESET
L1
NC_3
L9
NC_4
T7 F3
DDR3_DQSL
NC_6 DQSL
G3
DQSL DDR3_DQSLB
A9 C7
DDR3_DQSU
VSS_1 DQSU
B3 B7
VSS_2 DQSU DDR3_DQSUB
E1
VSS_3
G8 E7
DDR3_DML
VSS_4 DML
J2 D3
DDR3_DMU
VSS_5 DMU
J8
VSS_6
M1 E3 DDR3_DQL[0]
VSS_7 DQL0
M9 F7 DDR3_DQL[1]
VSS_8 DQL1
P1 F2 DDR3_DQL[2]
VSS_9 DQL2
P9 F8 DDR3_DQL[3]
VSS_10 DQL3
T1 H3 DDR3_DQL[4]
VSS_11 DQL4
T9 H8 DDR3_DQL[5]
VSS_12 DQL5
G2 DDR3_DQL[6]
DQL6
H7 DDR3_DQL[7]
DQL7
B1
VSSQ_1
B9 D7 DDR3_DQU[0]
VSSQ_2 DQU0
D1 C3 DDR3_DQU[1]
VSSQ_3 DQU1
D8 C8 DDR3_DQU[2]
VSSQ_4 DQU2
E2 C2 DDR3_DQU[3]
VSSQ_5 DQU3
E8 A7 DDR3_DQU[4]
VSSQ_6 DQU4
F9 A2 DDR3_DQU[5]
VSSQ_7 DQU5
G1 B8 DDR3_DQU[6]
VSSQ_8 DQU6
G9 A3 DDR3_DQU[7]
VSSQ_9 DQU7
Place near Memory
DDR3_A[0-13]
Place Close to DDR Pin
R9707
56
R9708
56
C9714
0.01uF
DDR3_MCK
50V
DDR3_MCKB
DDR3_CKE
+1.5V_FRC_DDR
R9706
510
DDR3_RESETB
DDR3_DQL[0-7]
DDR3_DQU[0-7]
Place the serail damping resistors
in the middle of DRAM pattern
R9709 22
FRC_DMU DDR3_DMU
R9710 22
FRC_DQSL DDR3_DQSL
R9711 22
FRC_DQSLB DDR3_DQSLB
R9712 22
FRC_DQSU DDR3_DQSU
R9713 22
FRC_DQSUB DDR3_DQSUB
R9714 22
FRC_DML DDR3_DML
R9715 22
FRC_ODT DDR3_ODT
R9716 22
FRC_RASB DDR3_RASB
R9717 22
FRC_CKE DDR3_CKE
R9718 22
FRC_MCLK DDR3_MCK
DDR3_MCK
R9719 22
FRC_MCLKB DDR3_MCKB
DDR3_MCKB
R9720 22
FRC_DDR3_RESETB DDR3_RESETB
AR9700
FRC_A[10] DDR3_A[10]
FRC_BA1 DDR3_BA1
FRC_A[12] DDR3_A[12]
FRC_A[4] DDR3_A[4]
22
AR9701
FRC_A[6] DDR3_A[6]
FRC_A[8] DDR3_A[8]
FRC_A[1] DDR3_A[1]
FRC_A[11] DDR3_A[11]
22
AR9702
FRC_A[0] DDR3_A[0]
FRC_A[2] DDR3_A[2]
FRC_A[13] DDR3_A[13]
FRC_A[9] DDR3_A[9]
22
AR9703
FRC_A[7] DDR3_A[7]
FRC_A[5] DDR3_A[5]
FRC_A[3] DDR3_A[3]
22
AR9704
FRC_BA2 DDR3_BA2
FRC_BA0 DDR3_BA0
FRC_WEB DDR3_WEB
FRC_CASB DDR3_CASB
22
LG1152 A0
URSA DDR3
AR9705
FRC_DQL[4] DDR3_DQL[4]
FRC_DQL[6] DDR3_DQL[6]
FRC_DQL[2] DDR3_DQL[2]
FRC_DQL[0] DDR3_DQL[0]
22
AR9706
FRC_DQU[5] DDR3_DQU[5]
FRC_DQU[3] DDR3_DQU[3]
FRC_DQU[7] DDR3_DQU[7]
FRC_DQU[1] DDR3_DQU[1]
22
AR9707
FRC_DQU[4] DDR3_DQU[4]
FRC_DQU[6] DDR3_DQU[6]
FRC_DQU[2] DDR3_DQU[2]
FRC_DQU[0] DDR3_DQU[0]
22
AR9708
FRC_DQL[3] DDR3_DQL[3]
FRC_DQL[1] DDR3_DQL[1]
FRC_DQL[5] DDR3_DQL[5]
FRC_DQL[7] DDR3_DQL[7]
22
2011. 02 .16
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LGE Internal Use Only