LG 42GA6400-UD Service Manual page 124

System Diagram – Focused on Digital Chip
L9A
DIF
Tuner ADC Demod
Audio
TS
ES
Display
CPU/GPU
AUD
PLL
HP out Headphone
Line out DAC
DAC
Audio L/R
Audio L/R
ADC
x6 ch
MIC ADC
SIF
Tuner AAD AFE
CVBS(CHB) AFE (CHB)
CVBS(x8ch) AFE (1ch)
Component AFE (3ch)
LVDS TX (HS)
LVDS TX (HS)
LVDS TX (HS)
HDMI RX
HDMI x4
MIXED IPs (Bus)
Line out DAC
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
L9D
STP out
TP in STP in
TP out (CI) (CHB)
SDCAS
SDCORE
TS
DES
TDES
2-channel
AES
time-shared
DVB-CSA
TP engine
SDIO
apes vpes
ADEC
Digital
PES PES PES
Audio output
DEC DEC DEC
Sound
DSP
VDEC VDEC
core core
DISP
IF
Audio
DSP
DEC ENC
JPEG JPEG
PNG
AAD
ADEC
(BTSC)
MAU
Display
LVDS RX (HS)
LVDS RX (HS)
LVDS RX (HS)
CVD
CVE
TE
Upload
TS
DVR
Download
MAU
vpes
SDEC
MAU
(thumbnail)
VDEC VENC
senc
PES
MCU
DEC
DEBLOCK
PESDEC
MAU
SPE VLC
MCU
QME CMC
HME
Core
IME MAU
PREP
PREP
MAU
CVD
ICOD
MAU
Global clock/reset/power mgt.
with PLL + DFT inside
DDR3
DCO
PLL
PLL
CRG CRG
+DFT +DFT
CPU DDR3
DCO
PLL PLL
Flexnoc (
Scaler(R) Scaler(L)
SMUX IPC(R) IPC(L)
NR(R) NR(L)
PRE3D
I2C x9 UART x3 SPI x2
DDR3 x16
I2C x12 UART x3 SPI x2
DDR3 PHY
DDRC SRAM
DMAC
SC
MCU
SP
ROM
OTP
- Dual-core CPU (CA9)
- Dual-core GPU (Mail400)
- Multiple MCU (x4)
- Multiple DSP (x2)
- Multiple DDR3 Channel (x3)
x MHz)
MCU
Scaler(sub) 2Dto3D PQ(R)
PQ(L)
SCI GPIO
SCI GPIO WDG Timer
APB Br
eMMC/SD eMMC/SD
USB x3 USB PHY USB x3
CI DVB-CI
SMC EB
GEM RGMII/RMII
NANDC NAND (SLC)
CA9
L2 $
JTAG
1MB
CA9
Mail400
PP
L2 $
VP
64KB
PP
GFX
DDR3
DDRC DDR3 PHY
x16
DDR3 PHY DDR3 x16
DDRC
DE
OSD
LVDS TX (HS) L9-3D
Right
OSD LVDS TX (HS) L9-3D
Left
LVDS TX (HS) L9-3D
LGE Internal Use Only