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Asus AAEON GENE-EHL5 User Manual

3.5” subcompact board
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GENE-EHL5
3.5" Subcompact Board
User's Manual 2
Ed
nd
Last Updated: May 26, 2022

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Summary of Contents for Asus AAEON GENE-EHL5

  • Page 1 GENE-EHL5 3.5” Subcompact Board User’s Manual 2 Last Updated: May 26, 2022...
  • Page 2 Copyright Notice This document is copyrighted, 2022. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of the original manufacturer.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp. ⚫ Intel, Pentium, and Celeron are registered trademarks of Intel Corporation ⚫ Intel Core is a registered trademark of Intel Corporation ⚫...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity GENE-EHL5 M16BT07020 (Heatsink) If any of these items are missing or damaged, please contact your distributor or sales representative immediately. Preface...
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document.
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON Main Board/ Daughter Board/ Backplane 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 ○ ○ ○ ○ ○ ○ 及其电子组件 外部信号 ○ ○ ○ ○ ○ ○ 连接器及线材...
  • Page 10 China RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Main Board/ Daughter Board/ Backplane Poisonous or Hazardous Substances or Elements Hexavalent Polybrominated Polybrominated Component Lead Mercury Cadmium Chromium Biphenyls Diphenyl Ethers (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB &...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Block Diagram ......................6 Chapter 2 – Hardware Information ..................7 Dimensions ....................... 8 Jumpers and Connectors ..................10 List of Jumpers ......................12 2.3.1 Clear CMOS Jumper (JP1) ................12 2.3.2 Touch Screen 4, 5, 8 Wire Selection (JP2) ..........
  • Page 12 2.4.10 LVDS/eDP Port (CN10) ................28 2.4.11 HDMI (CN11) ....................30 2.4.12 DP Port (CN13) ....................31 2.4.13 LAN (RJ-45) Port1 (CN14) ................33 2.4.14 LAN (RJ-45) Port2 (CN15)................34 2.4.15 SATA Port (CN16) ..................34 2.4.16 +5V Output for SATA HDD (CN17) ............35 2.4.17 Digital IO Port (CN18) ..................
  • Page 13 Electrical Specifications for I/O Port ..............56 Chapter 3 - AMI BIOS Setup ....................57 System Test and Initialization ................58 AMI BIOS Setup ..................... 59 Setup Submenu: Main ..................60 Setup Submenu: Advanced .................. 61 3.4.1 CPU Configuration ..................62 3.4.2 PCH-FW Configuration ................
  • Page 14 Setup Submenu: Save & Exit ................90 Chapter 4 – Driver Installation ....................91 Driver Download/Installation ................92 Appendix A - I/O Information ....................94 I/O Address Map ....................95 Memory Address Map ..................97 IRQ Mapping Chart ....................98 DMA Channel Assignments ................

  • Page 15: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 16: Specifications

    Specifications System FORM FACTOR 3.5" SubCompact Board Intel® Atom™ x6000E series, Intel® Pentium®, and Celeron® N and J series processors Intel® Atom™ x6425RE (4C/4T, 1.90GHz) Intel® Atom™ x6425E (4C/4C, 2.00GHz, up to 3.00GHz) Intel® Atom™ x6211E (2C/2T, 1.30GHz, up to 3.00GHz) Intel®...
  • Page 17 System RTC Battery Lithium Battery 3V/240mAh DIMENSION (L X W) 5.75" x 4" (146mm x 101.7mm) Power POWER REQUIREMENT +9-36V (Optional: +12V) POWER SUPPLY TYPE AT/ATX CONNECTOR Phoenix 2-pin Connector POWER CONSUMPTION TYPICAL: Intel Atom™ x6425E, DDR4 32GB, 3.26A @ +12V MAX: Intel Atom™...
  • Page 18 External I/O USB3.2 Gen 2 x 2 SERIAL PORT ━ VIDEO HDMI 2.0b x 1,DP1.4 x 1 (Optional VGA x 1) Internal I/O USB2.0 x 4 SERIAL PORT RS-232/422/485 x 4 VIDEO LVDS/eDP x 1 SATA SATA3.0 x 1,+5V SATA Power Connector x 1 AUDIO Audio Header x 1 DIO/GPIO...
  • Page 19 Expansion Default: PCIe x1, PCIe x 2 select by BIOS B-Key 3052 x 1 (USB3.2 Gen2) Others ━ Environment OPERATING TEMPERATURE 32°F ~ 140°F (0°C ~ 60°C) STORAGE TEMPERATURE -40°F ~ 176°F (-40°C ~ 80°C) OPERATING HUMIDITY 0% ~ 90% relative humidity, non-condensing MTBF (HOURS) 335,427 CE/FCC Class A...

  • Page 20: Block Diagram

    Block Diagram Chapter 1 – Product Specifications...

  • Page 21: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 22: Dimensions

    Dimensions Chapter 2 – Hardware Information...
  • Page 23 Chapter 2 – Hardware Information...

  • Page 24: Jumpers And Connectors

    Jumpers and Connectors Chapter 2 – Hardware Information...
  • Page 25 Chapter 2 – Hardware Information...

  • Page 26: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Label Function Clear CMOS Jumper Touch Screen 4/5/8-wire Mode Selection LVDS Port Backlight Inverter VCC Selection LVDS Port Operating VDD Selection LVDS Port Backlight Lightness Control Mode Selection Auto Power Button Enable/Disable Selection COM2 Pin8 Function Selection...

  • Page 27: Lvds Port Backlight Inverter Vcc Selection (Jp3)

    2.3.3 LVDS Port Backlight Inverter VCC Selection (JP3) +12V +5V (Default) 2.3.4 LVDS Port Operating VDD Selection (JP4) +3.3V (Default) 2.3.5 LVDS Port Backlight Lightness Control Mode Selection (JP5) VR Mode (Default) PWM Mode 2.3.6 Auto Power Button Enable/Disable Selection (JP6) 1 2 3 Disable Enable (Default)

  • Page 28: Com2 Pin8 Function Selection (Jp8)

    2.3.7 COM2 Pin8 Function Selection (JP8) Ring (Default) +12V 2.3.8 COM3 Pin8 Function Selection (JP9) Ring (Default) +12V 2.3.9 SMBUS/I2C Connector (JP11) Signal Type Signal Type SMBUS DATA / I2C DATA +3.3V SMBUS CLK / I2C CLK +1.8V SMBUS INT / INT SERIRQ Default: SMBUS.

  • Page 29: List Of Connectors

    List of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function Battery Touch Screen Connector Audio I/O Port Amplifier R-channel output Amplifier L-channel output M.2 B-Key 3052 (USB 3.2 GEN2 / USB 2.0) Nano SIM Card Socket M.2 B-Key 2242 (PCIe x2 or SATA III) LVDS/eDP Port Inverter / Backlight Connector...
  • Page 30 Label Function CN27 COM Port 1~4 CN31 SPI Program Port CN32 eSPI Deubg Port CN33 CPU FAN CN34 External Power Input CN35 External Power Input CN36 Front Panel CN37 PSE Connector CN38 CAN BUS CN39 VGA Port CN40 External +5VSB Input CN43 LAN1 SDP connector CN44...

  • Page 31: Battery (Cn1)

    2.4.1 Battery (CN1) Pin Name Signal Type Signal Level +3.3V 3.3V 2.4.2 Touch Screen Connector (CN2) 8 Wires Pin Name Signal Type Signal level TOP EXCITE BOTTOM EXCITE LEFT EXCITE RIGHT EXCITE TOP SENSE BOTTOM SENSE LEFT SENSE RIGHT SENSE Chapter 2 –...
  • Page 32 4 Wire Pin Name Signal Type Signal level BOTTOM LEFT RIGHT 5 Wires Pin Name Signal Type Signal level UL(Y) UR(H) LL(L) LR(X) SENSE(S) Note: Touch mode can be set by JP2 Chapter 2 – Hardware Information...

  • Page 33: Audio I/O Port (Cn3)

    2.4.3 Audio I/O Port (CN3) Pin Name Signal Type Signal level LINE_R_OUT MIC_R LINE_L_OUT MIC_L JD_LINE OUT JD_MIC IN GND_AUDIO GND_AUDIO JD_LINE IN LINE_R_IN +5V_AUDIO LINE_L_IN Chapter 2 – Hardware Information...

  • Page 34: Amplifier R-Channel Output (Cn4)

    2.4.4 Amplifier R-channel output (CN4) Pin Name Signal Type Signal level SKR_R+ SKR_R- 2.4.5 Amplifier L-channel output (CN5) Pin Name Signal Type Signal level SKR_L+ SKR_L- 2.4.6 M.2 Slot (B-Key 3052) (CN6) Pin Name Signal Type Signal level +3.3V +3.3V Chapter 2 –...
  • Page 35 Pin Name Signal Type Signal level +3.3V +3.3V USB_D+ DIFF W_DISABLE USB_D- DIFF SSD_DAS# USB_RX- DIFF UIM_RST USB_RX+ DIFF UIM_CLK UIM_DAT IN / OUT USB_TX- DIFF UIM_PWR USB_TX+ DIFF Chapter 2 – Hardware Information...
  • Page 36 Pin Name Signal Type Signal level DEVSLP GF_SM_CLK GF_SM_DAT IN / OUT PERST# PEWAKE# Chapter 2 – Hardware Information...
  • Page 37 Pin Name Signal Type Signal level +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V Chapter 2 – Hardware Information...

  • Page 38: Nano Sim Card Socket (Cn7)

    2.4.7 Nano SIM Card Socket (CN7) Pin Name Signal Type Signal level UIM_PWR UIM_RST UIM_CLK UIM_VPP UIM_DATA 2.4.8 M.2 Slot (B-Key 2242) (CN8) Pin Name Signal Type Signal level +3.3V +3.3V +3.3V +3.3V Chapter 2 – Hardware Information...
  • Page 39 Pin Name Signal Type Signal level W_DISABLE SSD_DAS# PCIE_RX- DIFF PCIE_RX+ DIFF PCIE_TX- DIFF PCIE_TX+ DIFF DEVSLP Chapter 2 – Hardware Information...
  • Page 40 Pin Name Signal Type Signal level PCIE0_RX- / SATA1_RX+ DIFF PCIE0_RX+ / SATA1_RX- DIFF PCIE0_TX- / SATA1_TX- DIFF PCIE0_TX+ / SATA1_TX+ DIFF PERST# CLKREQ# PCIE_CLK- PEWAKE# PCIE_CLK+ Chapter 2 – Hardware Information...
  • Page 41 Pin Name Signal Type Signal level +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V Note: The speed of PCIe for CN8 can be changed by BIOS and be changed to mSATA by BOM. Default: PCIe x2 Chapter 2 – Hardware Information...

  • Page 42: Lvds/Edp Port Inverter / Backlight Connector (Cn9)

    2.4.9 LVDS/eDP Port Inverter / Backlight Connector (CN9) Pin Name Signal Type Signal level BKL_PWR +5V / +12V BKL_PWR +5V / +12V BKL_CONTROL BKL_ENABLE Note1: LVDS BKL_PWR can be set to +5V or +12V by JP3 Note2: LVDS BKL_CONTROL can be set by JP5 2.4.10 LVDS/eDP Port (CN10) LVDS Function...
  • Page 43 Pin Name Signal Type Signal level LVDS_A_CLK- / EDP_LANE 3- DIFF LCD_PWR +3.3V/+5V LVDS_A_CLK+/ EDP_LANE 3+ DIFF LCD_PWR +3.3V/+5V LVDS_DA0- / EDP_LANE 2- DIFF LVDS_DA2- / EDP_LANE 0- DIFF LVDS_DA0+ / EDP_LANE 2+ DIFF LVDS_DA2+ / EDP_LANE 0+ DIFF LVDS_DA1- / EDP_LANE 1- DIFF LVDS_DA3- DIFF...

  • Page 44: Hdmi (Cn11)

    Pin Name Signal Type Signal level LVDS_DB1+ DIFF LVDS_DB2+ DIFF LVDS_B_CLK- DIFF LVDS_DB3- DIFF LVDS_B_CLK+ DIFF LVDS_DB3+ DIFF eDP HPD +3.3V Note: LVDS LCD_PWR can be set to +3.3V or +5V by JP4 2.4.11 HDMI (CN11) Pin Name Signal Type Signal level HDMI_D2+ DIFF...

  • Page 45: Dp Port (Cn13)

    Pin Name Signal Type Signal level HDMI_D1- DIFF HDMI_D0+ DIFF HDMI_D0- DIFF HDMI_CLK+ DIFF HDMI_CLK- DIFF HDMI_SLK HDMI_SDA IN/OUT HPLG_DETECT 2.4.12 DP Port (CN13) Pin Name Signal Type Signal level DP_D0+ DIFF Chapter 2 – Hardware Information...
  • Page 46 Pin Name Signal Type Signal level DP_D0- DIFF DP_D1+ DIFF DP_D1- DIFF DP_D2+ DIFF DP_D2- DIFF DP_D3+ DIFF DP_D3- DIFF DDI2_OB_AUX_EN DP_AUX+ / DDI2_CTRL_CLK DIFF DP_AUX- / DDI2_CTRL_DATA DIFF HPLG_DETECT +3.3V +3.3V Chapter 2 – Hardware Information...

  • Page 47: Lan (Rj-45) Port1 (Cn14)

    2.4.13 LAN (RJ-45) Port1 (CN14) ACT/LINK SPEED Pin Name Signal Type Signal level MDI0+ DIFF MDI0- DIFF MDI1+ DIFF MDI2+ DIFF MDI2- DIFF MDI1- DIFF MDI3+ DIFF MDI3- DIFF Chapter 2 – Hardware Information...

  • Page 48: Lan (Rj-45) Port2 (Cn15)

    2.4.14 LAN (RJ-45) Port2 (CN15) ACT/LINK SPEED Pin Name Signal Type Signal level MDI0+ DIFF MDI0- DIFF MDI1+ DIFF MDI2+ DIFF MDI2- DIFF MDI1- DIFF MDI3+ DIFF MDI3- DIFF 2.4.15 SATA Port (CN16) Pin Name Signal Type Signal level SATA_TX+ DIFF SATA_TX- DIFF...

  • Page 49: Output For Sata Hdd (Cn17)

    Pin Name Signal Type Signal level SATA_RX+ DIFF 2.4.16 +5V Output for SATA HDD (CN17) Pin Name Signal Type Signal level 2.4.17 Digital IO Port (CN18) Pin Name Signal Type Signal level DIO1 DIO0 DIO3 DIO2 DIO5 DIO4 Chapter 2 – Hardware Information...

  • Page 50: Digital Io Port (Cn19)

    Pin Name Signal Type Signal level DIO7 DIO6 2.4.18 Digital IO Port (CN19) Pin Name Signal Type Signal level DIO9 DIO8 DIO11 DIO10 DIO13 DIO12 DIO15 DIO14 Chapter 2 – Hardware Information...

  • Page 51: Usb 3.1 Ports (Cn20)

    2.4.19 USB 3.1 Ports (CN20) Pin Name Signal Type Signal level +5VSB USB_D- DIFF USB_D+ DIFF USB_SSRX− DIFF USB_SSRX+ DIFF USB_SSTX− DIFF USB_SSTX+ DIFF +5VSB USB_D- DIFF USB_D+ DIFF USB_SSRX− DIFF USB_SSRX+ DIFF USB_SSTX− DIFF USB_SSTX+ DIFF Chapter 2 – Hardware Information...

  • Page 52: Usb 2.0 Port (Cn21)

    2.4.20 USB 2.0 Port (CN21) Pin Name Signal Type Signal level +5VSB +5VSB USB_D0- DIFF USB_D1- DIFF USB_D0+ DIFF USB_D1+ DIFF 2.4.21 USB 2.0 Port (CN22) Pin Name Signal Type Signal level +5VSB +5VSB Chapter 2 – Hardware Information...

  • Page 53: Slot (B-Key 2280) (Cn25)

    Pin Name Signal Type Signal level USB_D0- DIFF USB_D1- DIFF USB_D0+ DIFF USB_D1+ DIFF 2.4.22 M.2 Slot (B-Key 2280) (CN25) Pin Name Signal Type Signal level +3.3V +3.3V +3.3V +3.3V USB_D8+ DIFF W_DISABLE USB_D8- DIFF SSD_DAS# Chapter 2 – Hardware Information...
  • Page 54 Pin Name Signal Type Signal level PCIE7_RX- DIFF PCIE7_RX+ DIFF PCIE7_TX- DIFF PCIE7_TX+ DIFF PCIE6_RX- DIFF PCIE6_RX+ DIFF Chapter 2 – Hardware Information...
  • Page 55 Pin Name Signal Type Signal level PCIE6_TX- DIFF PCIE6_TX+ DIFF PERST# CLKREQ# PCIE1_CLK- PEWAKE# PICE1_CLK+ +3.3V +3.3V Chapter 2 – Hardware Information...

  • Page 56: Slot (E-Key 2230) (Cn26)

    Pin Name Signal Type Signal level +3.3V +3.3V +3.3V +3.3V Note: The speed of PCIe for CN25 can be changed by BIOS. Default: PCIe x1 2.4.23 M.2 Slot (E-Key 2230) (CN26) Pin Name Signal Type Signal level +3.3V +3.3V USB_D+ DIFF +3.3V +3.3V...
  • Page 57 Pin Name Signal Type Signal level BT_PCM_IN BT_PCM_OUT_CLKREQ PCIE1_TX+ DIFF PCIE1_TX- DIFF PCIE1_RX+ DIFF PCIE1_RX- DIFF Chapter 2 – Hardware Information...
  • Page 58 Pin Name Signal Type Signal level PCIE0_CLK+ DIFF PCIE0_CLK- DIFF RESET# 3.3V PCIE_CLKREQ# BT_EN 3.3V PCIE_WAKE# 3.3V WIFI_EN 3.3V I2C_DATA IN / OUT 3.3V I2C_CLK 3.3V ALERT# 3.3V Chapter 2 – Hardware Information...

  • Page 59: Com Port 1~4 (Cn27)

    Pin Name Signal Type Signal level +3.3V +3.3V +3.3V +3.3V 2.4.24 COM Port 1~4 (CN27) RS-232/422/485 Pin Name Signal Type Signal level COM1 : DCD / RS422_TX-/ RS485_D- IN / OUT ±5V COM2 : DCD / RS422_TX-/ RS485_D- IN / OUT ±5V COM1: RX / RS422_TX+ / RS485_D+ IN / OUT...
  • Page 60 Pin Name Signal Type Signal level COM1: RTS ±5V COM2: RTS ±5V COM1: CTS COM2: CTS COM1: RI IN/ PWR +5V/+12V COM2: RI/+5V/+12V IN/ PWR +5V/+12V COM3 : DCD / RS422_TX-/ RS485_D- IN / OUT ±5V COM4 : DCD / RS422_TX-/ RS485_D- IN / OUT ±5V COM3: RX / RS422_TX+ / RS485_D+ IN / OUT...

  • Page 61: Espi Debug Port (Cn32)

    Pin Name Signal Type Signal level 2.4.25 eSPI Debug Port (CN32) Pin Name Signal Type Signal level ESPI_IO0 +1.8V ESPI_IO1 +3.3V ESPI_IO2 +3.3V ESPI_IO3 +3.3V +3.3V +3.3V ESPI_CS# ESPI_RST# +3.3V ESPI_CLK +3.3V +3.3V Chapter 2 – Hardware Information...

  • Page 62: Cpu Fan (Cn33)

    2.4.26 CPU FAN (CN33) Pin Na me Signal Type Signal level FAN_POWER +12V FAN_TAC FAN_CTL 2.4.27 External Power Input (CN34) +12V GND Pin Name Signal Type Signal level +12V +9~+36V (or +12V) 2.4.28 External Power Input (CN35) Pin Name Signal Type Signal level +12V +9~+36V (or +12V)

  • Page 63: Front Panel Connector (Cn36)

    2.4.29 Front Panel Connector (CN36) Function Function PWR_BTN- PWR_BTN+ HDD_LED- HDD_LED+ SPEAKER- SPEAKER+ PWR_LED- PWR_LED+ H/W RESET- H/W RESET+ 2.4.30 PSE Connector (CN37) Pin Name Signal Type Signal level PSE_POWER 1.8V / 3.3V PSE_TRACE_CLK PSE_SW_DIO PSE_TRACE_DATA0 IN/ OUT PSE_SW_CLK PSE_TRACE_DATA1 IN/ OUT Chapter 2 –...

  • Page 64: Can Bus (Cn38)

    Pin Name Signal Type Signal level PSE_TRACE_SWO PSE_TRACE_DATA2 IN/ OUT RESET# PSE_TRACE_DATA3 IN/ OUT UART_TX UART_RX 2.4.31 CAN BUS (CN38) Pin Name Signal Type Signal level CAN_BUS_0_H IN / OUT CAN_BUS_0_L IN / OUT CAN_BUS_1_H IN / OUT CAN_BUS_1_L IN / OUT Chapter 2 –...

  • Page 65: Vga Port (Cn39)

    2.4.32 VGA Port (CN39) Pin Name Signal Type Signal level GREEN BLUE RED_GND_RTN GREEN_GND_RTN BLUE_GND_RTN DDC_DATA HSYNC VSYNC DDC_CLK Chapter 2 – Hardware Information...

  • Page 66: External +5Vsb Input (Cn40)

    2.4.33 External +5VSB Input (CN40) Pin Name Signal Type Signal level PS_ON# +3.3V +5VSB 2.4.34 LAN1 SDP Connector (CN43) Pin Name Signal Type Signal level SDP0 IN / OUT SDP0 IN / OUT SDP0 IN / OUT SDP0 IN / OUT Chapter 2 –...

  • Page 67: Lan2 Sdp Connector (Cn44)

    2.4.35 LAN2 SDP Connector (CN44) Pin Name Signal Type Signal level SDP0 IN / OUT SDP0 IN / OUT SDP0 IN / OUT SDP0 IN / OUT 2.4.36 DDR4 SO-DIMM (DIMM1) Standard Version Chapter 2 – Hardware Information...

  • Page 68: Thermal Solution

    Thermal Solution Chapter 2 – Hardware Information...
  • Page 69 Chapter 2 – Hardware Information...

  • Page 70: Electrical Specifications For I/O Port

    Electrical Specifications for I/O Port Reference Signal Name Rate Output Audio I/O Port +5V/0.5A M.2 B-Key 3052 +3.3VSB +3.3V/2.0A M.2 B-Key 2242 +3.3VSB +3.3V/1.5A LVDS / eDP Port Inverter / +5V/+12V +5V/2.0A or +12V/2.0A Backlight Connector LVDS /eDP Port CN10 +3.3V/+5V +3.3V/1.5A or +5V/1.5A HDMI port...

  • Page 71: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 72: System Test And Initialization

    System Test and Initialization The GENE-CML5 board uses certain routines to perform testing and initialization during the boot up sequence. If an error, fatal or non-fatal, is encountered, the module will output a few short beeps or display an error message. The module can usually continue the boot up sequence with non-fatal errors.

  • Page 73: Ami Bios Setup

    AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press <Del>...

  • Page 74: Setup Submenu: Main

    Setup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 75: Setup Submenu: Advanced

    Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 76: Cpu Configuration

    3.4.1 CPU Configuration Options summary: Active Processor Optimal Default, Failsafe Default Cores Number of cores to enable in each processor package. Intel (VMX) Disabled Virtualization Enabled Optimal Default, Failsafe Default Technology When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.

  • Page 77: Pch-Fw Configuration

    3.4.2 PCH-FW Configuration Chapter 3 – AMI BIOS Setup...

  • Page 78: Firmware Update Configuration

    3.4.2.1 Firmware Update Configuration Options summary: Me FW Image Enabled Re-Flash Disabled Optimal Default, Failsafe Default Enable/Disable Me FW Image Re-Flash function. FW Update Disabled Enabled Optimal Default, Failsafe Default Enable/Disable ME FW Update function. Chapter 3 – AMI BIOS Setup...

  • Page 79: Trusted Computing

    3.4.3 Trusted Computing Options summary: Security Deice Enable Optimal Default, Failsafe Default Support Disable Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. SHA-1 PCR Bank Disabled Optimal Default, Failsafe Default Enabled...
  • Page 80 Enable or Disable SHA384 PCR Bank. SM3_256 PCR Bank Enabled Optimal Default, Failsafe Default Disabled Enable or Disable SM3_256 PCR Bank Pending operation None Optimal Default, Failsafe Default TPM Clear Schedule an Operation for the Security Device. NOTE: Your Computer will reboot during restart in order to change State of Security Device.
  • Page 81 Device Select Auto Optimal Default, Failsafe Default TPM 1.2 TPM 2.0 TPM 1.2 will restrict support to TPM 1.2 devices, TPM 2.0 will restrict support to TPM 2.0 devices, Auto will support both with the default set to TPM 2.0 devices if not found, TPM 1.2 devices will be enumerated.

  • Page 82: Sata Configuration

    3.4.4 SATA Configuration Options summary: SATA Controller(s) Enabled Optimal Default, Failsafe Default Disabled Enable/Disable SATA Device. Port* Enabled Optimal Default, Failsafe Default Disabled Enable or Disable SATA Port. Chapter 3 – AMI BIOS Setup...

  • Page 83: Hardware Monitor

    3.4.5 Hardware Monitor Options summary: Smart Fan Disable Enable Optimal Default, Failsafe Default Enables or Disables Smart Fan. Chapter 3 – AMI BIOS Setup...

  • Page 84: Smart Fan Mode Configuration

    3.4.5.1 Smart Fan Mode Configuration Options summary: FAN1 Output Mode Output PWM mode (open drain) Linear Fan Application Output PWM mode (push Optimal Default, Failsafe Default pull) Fan 1 Smart Fan Manual Duty Mode Control Auto Duty-Cycle Mode Optimal Default, Failsafe Default Smart Fan Mode Select Temperature Source CPU(PECI) Temperature System Temperature...
  • Page 85 Temperature 1 Duty Cycle 1 Auto fan speed control. Fan speed will follow different temperature by different duty cycle 1-100 Chapter 3 – AMI BIOS Setup...

  • Page 86: Sio Configuration

    3.4.6 SIO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 87: Serial Port Configuration

    3.4.6.1 Serial Port Configuration Options summary: Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=3F8h; IRQ=4 IO=2F8h; IRQ=3 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 88: Serial Port Console Redirection

    3.4.7 Serial Port Console Redirection Options summary: Console Redirection Disabled Optimal Default, Failsafe Default Enabled Console Redirection Enable or Disable. Console Redirection Disabled Optimal Default, Failsafe Default Enabled Console Redirection Enable or Disable. Chapter 3 – AMI BIOS Setup...

  • Page 89: Scs Configuration

    3.4.8 SCS Configuration eMMC 5.1 Controller Disabled Enabled Optimal Default, Failsafe Default Enable or Disable SCS eMMC 5.1 Controller. eMMC 5.1 HS400 Disabled Mode Enabled Optimal Default, Failsafe Default Enable or Disable SCS eMMC 5.1 HS400 Mode Enable HS400 Disabled Optimal Default, Failsafe Default software tuning Enabled...

  • Page 90: Power Management

    3.4.9 Power Management Options summary: Power Mode ATX Type Optimal Default, Failsafe Default AT Type Select power supply mode. Restore AC Last State Optimal Default, Failsafe Default Power Loss Always On Always Off Select power state when power is re-applied after a power failure. RTC wake system Disable Optimal Default, Failsafe...

  • Page 91: Digital Io Port Configuration

    3.4.10 Digital IO Port Configuration Options summary: DIO Port* Output Input Set DIO as Input or Output Output Level High Set output level when DIO pin is output Chapter 3 – AMI BIOS Setup...

  • Page 92: Setup Submenu: Chipset

    Setup Submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 93: System Agent (Sa) Configuration

    3.5.1 System Agent (SA) Configuration Options summary: VT-d Disabled Enabled Optimal Default, Failsafe Default VT-d capability Chapter 3 – AMI BIOS Setup...

  • Page 94: Memory Configuration

    3.5.1.1 Memory Configuration Options summary: In-Band ECC Disabled Optimal Default, Failsafe Default Enabled Enable/Disable In-Band ECC Chapter 3 – AMI BIOS Setup...

  • Page 95: Lvds Panel Configuration

    3.5.1.2 LVDS Panel Configuration Options summary: LVDS Disabled Enabled Optimal Default, Failsafe Default Enable/Disabled this panel. LVDS Panel Type 640x480,18bit,60Hz 800x480,18bit,60Hz 800x600,18bit,60Hz 1024x600,18bit,60Hz 1024x768,18bit,60Hz 1024x768,24bit,60Hz Optimal Default, Failsafe Default 1280x768,24bit,60Hz 1280x1024,48bit,60Hz 1366x768,24bit,60Hz Chapter 3 – AMI BIOS Setup...
  • Page 96 1440x900,48bit,60Hz 1600x1200,48bit,60Hz 1920x1080,48bit,60Hz 1920x1200,48bit,60Hz Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item. Panel Mode Single Channel Optimal Default, Failsafe Default Dual Channel Panel mode selection for Single channel or Dual channel Color Depth 18-bit Optimal Default, Failsafe Default 24-bit 36-bit...

  • Page 97: Setup Submenu: Security

    Setup Submenu: Security Change User/Administrator Password You can set an Administrator Password or User Password. An Administrator Password must be set before you can set a User Password. The password will be required during boot up, or when the user enters the Setup utility. A User Password does not provide access to many of the features in the Setup utility.

  • Page 98: Secure Boot

    3.6.1 Secure Boot Secure Boot Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key(PK) is enrolled and the System is in User mode. The mode change requires platform reset Secure Boot Mode Custom Optimal Default, Failsafe Default Standard Secure Boot mode options: Standard or Custom.

  • Page 99: Key Management

    3.6.1.1 Key Management Options summary: Factory Key Disabled Optimal Default, Failsafe Default Provision Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key(PK) is enrolled and the System is in User mode. The mode change requires platform reset Restore Factory Keys Force System to User Mode.
  • Page 100 Allow the image to run in Secure Boot mode. Enroll SHA256 Hash certificate of a PE image into Authorized Signature Database (db) Remove 'UEFI CA' from DB Device Guard ready system must not list 'Microsoft UEFI CA' Certificate in Authorized Signature database (db) Restore DB defaults Restore DB variable to factory defaults...
  • Page 101 Append OsRecovery Signatures Update Append Enroll Factory Defaults or load certificates from a file: 1.Public Key Certificate: a)EFI_SIGNATURE_LIST b)EFI_CERT_X509 (DER) c)EFI_CERT_RSA2048 (bin) d)EFI_CERT_SHAXXX 2.Authenticated UEFI Variable 3.EFI PE/COFF Image(SHA256) Key Source: Factory,External,Mixed Chapter 3 – AMI BIOS Setup...

  • Page 102: Setup Submenu: Boot

    Setup Submenu: Boot Options summary: Quiet Boot Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Quiet Boot option. UEFI PXE Support Disabled Optimal Default, Failsafe Default Enabled Enable/Disable UEFI Network Stack. FIXED BOOT ORDER Priorities Sets the system boot order Chapter 3 –...

  • Page 103: Bbs Priorities

    3.7.1 BBS Priorities Chapter 3 – AMI BIOS Setup...

  • Page 104: Setup Submenu: Save & Exit

    Setup Submenu: Save & Exit Options summary: Save Changes and Reset Reset the system after saving the changes. Discard Changes and Exit Exit system setup without saving any changes. Restore Defaults Restore/Load Default values for all the setup options. Chapter 3 – AMI BIOS Setup...

  • Page 105: Chapter 4 - Driver Installation

    Chapter 4 Chapter 4 – Driver Installation...

  • Page 106: Driver Download/Installation

    Driver Download/Installation Drivers for the GENE-EHL5 can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/subcompact-boards-gene-ehl5 Download the driver(s) you need and follow the steps below to install them. Step 1 – Install Chipset Drivers Open the Intel Chipset folder Run the SetupChipset.exe in the folder Follow the instructions...
  • Page 107 Step 4 – Install Audio Driver Open the Audio folder Run the Setup.exe file in the folder Follow the instructions Drivers will be installed automatically Step 5 – Install Serial IO Drivers Open the Serial IO folder Follow the instructions Drivers will be installed automatically Step 6 –...

  • Page 108: Appendix A - I/O Information

    Appendix A Appendix A - I/O Information...

  • Page 109: I/O Address Map

    I/O Address Map Appendix A – I/O Information...
  • Page 110 Appendix A – I/O Information...

  • Page 111: A.2 Memory Address Map

    A.2 Memory Address Map Appendix A – I/O Information...

  • Page 112: A.3 Irq Mapping Chart

    A.3 IRQ Mapping Chart Appendix A – I/O Information...
  • Page 113 Appendix A – I/O Information...

  • Page 114: A.4 Dma Channel Assignments

    A.4 DMA Channel Assignments Appendix A – I/O Information...

  • Page 115: Appendix B - Mating Connectors And Cables

    Appendix B Appendix B – Mating Connectors and Cables...

  • Page 116: Mating Connectors And Cables

    Mating Connectors and Cables Mating Connector Connector Available Function Cable P/N Label Cable Vendor Model no RTC Battery Molex 51021-0200 Battery Cable 175011301C Touch Screen SHR-9V-S-B Connector HSG:11002H0 Audio IO 0-2*6P JCTC Audio Cable 170X000156 Port TER:11002TO P-2E Amplifier R-channel Molex 51021-0200 output...
  • Page 117 Mating Connector Connector Available Function Cable P/N Label Cable Vendor Model no +5V Output SATA Power CN17 for SATA PHR-2 1702150155 Cable CN18 Digital IO 50247-010H0 ACES CN19 Port H0-001 CN21 50247-010H0 USB 2.0 Port ACES USB2.0 Cable 170010010D CN22 H0-001 HSG:11002H0 COM Port...

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