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EVALUATION BOARD MANUAL
2.1.7
ADC BLOCK
4
5
① J1: ADC input connector
② J2, J3, J4: J2, J3 and J4 are selected to sample test with AIN0, AIN1 and AIN2
③ RV1: Variable Resistor
④ J24: ADC Power Source
Close: When connecting (short), AVDD is same to VDD33.
Open: AVDD is a second (right) pin of J24. So, AVDD should be connected to another power.
⑤ J7: 2,3 connection - ADTRG signal is generated by SW4
⑥ SW11, SW12: Control cap for each ADC input port.
1
S3F401F_BD_UM_REV1.00
2
⑥
3
14
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