ASROCK FATALITY Z370 User Manual page 79

Write to Read Delay (tWTR_L)
he number of clocks between the last valid write operation and the next read command to
the same internal bank.
Write to Read Delay (tWTR_S)
he number of clocks between the last valid write operation and the next read command to
the same internal bank.
Read to Precharge (tRTP)
he number of clocks that are inserted between a read command to a row pre-
charge command to the same rank.
Four Activate Window (tFAW)
he time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL)
Conigure CAS Write Latency.
Third Timing
tREFI
Conigure refresh cycles at an average periodic interval.
tCKE
Conigure the period of time the DDR4 initiates a minimum of one refresh
command internally once it enters Self-Refresh mode.
tRDRD_sg
Conigure between module read to read delay.
tRDRD_dg
Conigure between module read to read delay.
tRDRD_dr
Conigure between module read to read delay.
tRDRD_dd
Conigure between module read to read delay.
tRDWR_sg
Conigure between module read to write delay.
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