Yamaha Clavinova CLP-110 Service Manual page 16

CLP-110
G UPD63200GS-E1 (XP867A00) DAC (Digital to Analog Converter)
PIN
NAME I/O FUNCTION
NO.
1 4/8
I 4/8 Fs selection
2 D.GND Digital ground
3 16 BIT I 16bit/18bit selection
4 D.GND Digital power supply
5 A,GND Analog ground
6 R.OUT O Channel R output
7 A.VDD
Analog power supply
8 A.VDD
G YMZ702-D (XR632A00) KSN2 (Key Scanner)
PIN
NAME I/O FUNCTION
NO.
1 BK5 O
2 BK4 O
3 BK3 O
Key block (open drein)
4 BK2 O
5 BK1 O
6 BK0 O
7 MK15 I
8 MK14 I
9 MK13 I
First make contact
10 MK12 I
11 MK11 I
12 MK10 I
13 MK05 I
14 MK04 I
15 MK03 I
Second make contact
16 MK02 I
17 MK01 I
18 MK00 I
19 XIN I Crystal osc. input (4 MHz)
20 XOUT O Crystal osc. output (4 MHz)
I IC BLOCK DIAGRAM
2+"#% /
µ (XF291A00)
Dual Operational Amplifier
Output A 1
Inverting
2
Input A
- +
Non-Inverting
3
Input A
-DC Voltage Supply 4 -V
16
M5227FP (XT773A00)
Graphic Equalizer
AM: IC007
+DC Voltage
+V 8
Supply
7 Output B
Inverting
6
+ -
Input B
Non-Inverting
5
Input B
PIN
NAME I/O FUNCTION
NO.
9 R.REF Channel R voltage reference
10 L.REF Channel L voltage reference
11 L.OUT O Channel L output
12 A.GND I Analog ground
19 WDCK I Word clock
20 RSI I Channel R series input
21 SI/LSI I Series input/Channel L series input
22 CLK I Clock
PIN
NAME I/O FUNCTION
NO.
21 GND Ground
22 VDD Power supply
23 SO O Serial data
24 ACK I Acknowledge/mode select
25 XCK I Clock for serial data
26 /IC I Initial clear
27 TST1 I Test mode
28 TST2 I (L,L: normal mode, others: test)
29 XCKINH I Inhibit of serial clock
30 BK14 O
31 BK13 O
32 BK12 O
33 BK11 O
34 BK10 O Key block (open drein)
35 BK9 O
36 BK8 O
37 BK7 O
38 BK6 O
39 GND Ground
40 VDD Power supply
AM: IC004, 005
47k
1 16
IN1 -Vcc
10k
2
15
NF1 GND
540
10k
47k
3
14
IN2 +Vcc
4
13
NF2 OUT
540
+ -
540 47k
5 12
IN3 -IN
6 11
NF3 +IN
47k
540
47k 540
7
10
IN4 NF5
+ -
8
9
NF4 IN5
540 47k
DM: IC004
GHDcl SW L: KSN2
SN74HC132NSR (XW792A00)
MM74HC132SJX (XY352A00)
Quad 2 Input NAND
1A 1 14 VDD
1B 2 13 4B
1Y 3 12 4A
2Y 4 11 4Y
2A 5 10 3Y
2B 6 9 3B
GND 7 8 3A
DM: IC009