TTE Tech A664 Lab v2.0 User Manual page 10

2. OVERVIEW
route specifies to which ports such frames can be routed. If no port is configured, these frames are
dropped.
TTEthernet implementation
• 8 sub-schedules
• 8 clock synchronization masters
• 4096 virtual links
• Store-and-forward switch architecture
ARINC 664 p7 implementation
• Policing, filtering, switching engine for band-width control and traffic prioritizing
• Integrity checking and error checking of frames
• 4096 virtual links with up to 8 priorities, with restrictions of their associated ports
• 4096 BAGs
• BAGs freely configurable from 0.01 to 1310 ms
• BAG configuration granularity 100 µs
• Jitter and BAG resolution of 8 ns
• The switch supports ICMP (ping), SNMP v1 and A615A-3.
• Configuration data programmable via ARINC 615A/TFTP
Physical specifications
• 19-inch rack housing, 1 height unit (1U)
Power supply
• 110-230 V, 50/60 Hz
• 0.8 A max. current
Environmental operating ranges
• Operating temperature: 0
Standards compliance
• IEEE 802.3™-2005 (switching, flow control) [6].
• IEEE 802.1Q™-2011 [4]
• IEEE 1588-2008: The switch supports the IEEE 1588 end-to-end transparent clock mode. The clock
of the switch is not synchronized to the IEEE 1588 Master Clock [5].
• ARINC Specification 664P7-1: The switch is fully compliant with ARINC 664 part 7 (deterministic
Ethernet networking) [2].
• SAE AS 6802: The switch supports the SAE AS 6802 network synchronization and start-up mecha-
nism (fault-tolerant TTEthernet clock synchronization protocol) [7].
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Document Number:
D-A664Lab-G-05-001