Lsi Pin Description （Lsi 端子機能表 - Yamaha P-105B Service Manual

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LSI PIN DESCRIPTION （LSI 端子機能表）
CONTENTS （目次）
• R8A02042BG (YC479A00) SWX08
• SWL01U (YA876A01) CPU
• μPD789022GB-A15-8E (XZ560100) CPU (MKS)
• WM8524GEDT/R (YC681B00) DAC
• YDA175 (YD822A00) DIGITAL POWER AMPLIFIER
• YDA175 (YD822A00) DIGITAL POWER AMPLIFIER
PIN
*1)
NAME I/O
NO.
1 REFA AO
2 AVSS GND
3 N.C. –
4 DVSS GND
5 MCK I
6 SDATA I
7 SCLK I
8 LRCLK I
9 PVDDPR PVDD power Power for the digital amplifier
10 OUTPR O
11 OUTPR O
12 PVSSR GND
13 PVSSR GND
14 OUTMR O
15 OUTMR O
16 PVDDMR PVDD power Power for the digital amplifier
17 SLEEPN I
18 PROTN O/D
*1): I: Input pin, O: Output pin, A: Analog pin, O/D: Open-Drain output pin.
Note
PVDD power pins should be connected each other on the boards. Likewise, GND pins should be also connected each other on it.
Each output pin with the same name (OUTPR, OUTMR, OUTPL and OUTML) should be connected on the board.
*2): A voltage for supplying SLEEP pin with H level should be applied from an external power supply. Do not apply from REFA pin output.
P-105B/P-105WH
FUNCTION
Internal Regulator Output
Analog GND
No Connection Pin. This pin must
be left open or connected to GND.
Digital GND
Master Clock Input Pin
Audio Data Input Pin
Bit Clock Input Pin
Word Clock Input Pin
output (Rch+)
Digital Amplifier Output (Rch+)
Digital Amplifier Output (Rch+)
GND for the digital amplifier
output (Rch)
GND for the digital amplifier
output (Rch)
Digital Amplifier Output (Rch-)
Digital Amplifier Output (Rch-)
output (Rch-)
*2)
Sleep Reset pin
Error Flag Output Pin
P-105B/P-105WH/P-35B/L-85WH/LP-5AWH
P-105B/P-105WH ............................................26
......................................................28
P-35B
............................................30
P-105B/P-105WH
P-105B/P-105WH
P-105B/P-105WH
P-35B
DM: IC22 [P-105B/P-105WH], IC302 [P-35B]
PIN
*1)
NAME I/O
NO.
19 N.C. –
20 N.C. –
21 N.C. –
22 CKMOD I
23 TEST –
24 MUTEN I
25 PVDDML PVDD power Power for the digital amplifier
26 OUTML O
27 OUTML O
28 PVSSL GND
29 PVSSL GND
30 OUTPL O
31 OUTPL O
32 PVDDPL PVDD power Power for the digital amplifier
P-35B ......................30
......................25
P-35B
FUNCTION
No Connection Pin. This pin must
be left open or connected to GND.
No Connection Pin. This pin must
be left open or connected to GND.
No Connection Pin. This pin must
be left open or connected to GND.
Clock Mode Setting Pin
Test Pin. This pin must
be connected to GND.
Mute pin
output (Lch-)
Digital Amplifier Output (Lch-)
Digital Amplifier Output (Lch-)
GND for the digital amplifier output
GND for the digital amplifier output
Digital Amplifier Output (Lch+)
Digital Amplifier Output (Lch+)
output (Lch+)
(Lch)
(Lch)
25