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IC BLOCK DIAGRAM & DESCRIPTION
IC441 TC9422F (Volume Control)
INPUT
SELECTOR
2
L-IN1
L-IN2
3
L-IN3
4
L-IN4
5
L-SW-OUT
6
L-VR-IN
7
L-B1
8
L-B2
9
10
L-B3
L-Tone-OUT
11
500
12
L-T1
IC601 PT6315 (VFD Driver / Controller IC)
Control
7
DIN
Serial
6
DOUT
Data
CLK
8
Display Memory
Interface
(24 bits x 17 Words)
9
STB
TI~inc Generator
OSC
5
OSC
Key Moter Memory
LED1
1
LED
LED2
2
Driver
3
LED3
LED4
4
10
K1
All manuals and user guides at all-guides.com
GND
1
100k
GAIN CONTROL
0, 6, 12, 18dB
MAIN VR
50k / 64STEP
50k
CAPACITOR FOR
OSCILLATION
BASS VR
50k /
16STEP
13k
TREBLE VR
50k /
16STEP
750
50k
50k
13
Vref
Driving Circuit
11
13
30
K2
VDD
GND
VEE
V
DD
28
GAIN CONTROL
0, 6, 12, 18dB
MAIN VR
50k / 64STEP
BASS VR
50k /
16STEP
TREBLE VR
50k /
16STEP
32BIT SR
14
15
16
CK
DATA
STB
14
SG1/KS1
15
SG2/KS2
Pin Name
SG3/KS3
16
17
SG4/KS4
LED1 to LED4
18
SG5/KS5
OSC
19
SG6/KS6
20
Segment
SG7/KS7
Driver
21
SG8/KS8
DOUT
22
SG9/KS9
Grid
Driver
23
SG10/KS10
24
SG11/KS11
Key Scan
(Schmitt Trigger)
25
SG12/KS12
Output
26
SG13/KS13
27
SG14/KS14
(Schmitt Trigger)
28
SG15/KS15
30
SG16/KS16
31
SG17/GR12
(Schmitt Trigger)
32
SG18/GR11
33
SG19/GR10
K1 to K2
34
SG20/GR9
35
SG21/GR8
VSS
36
SG22/GR7
VDD
37
SG23/GR6
38
SG24/GR5
SG1/KS1 to
SG16/KS16
42
GR1
VEE
41
GR2
Grid
SG17/GR12 to
Driver
40
GR3
SG24/GR5
39
GR4
GR4 to GR1
- 16 -
INPUT
SELECTOR
100k
27
R-IN1
26
R-IN2
25
R-IN3
24
R-IN4
23
R-SW-OUT
22
R-VR-IN
21
R-B1
50k
20
R-B2
19
R-B3
CAPACITOR FOR
OSCILLATION
18
R-Tone-OUT
500
13k
17
R-T1
750
I/O
Description
O
LED Output Pin
Oscillator Input Pin
I
A resistor is connected to this pin to
determinc the oscillation frequency
Data Output Pin (N-Channel, Open-Drain)
O
This pin outputs scrial data at the falling
edge of the shift clock
(starting from the lower bit)
Data Input Pin
DIN
I
This pin inputs serial data at the rising edge
of the shift clock (starting from the lower bit)
Clock Input Pin
CLK
I
This pin reads serial data at the rising edge
and outputs data at the falling edge.
Serial Interface Strobe Pin
STB
The data input after the STB has fallen is
I
processed as a command.
When this pin "HIGH",CLK is ignored,
Key Data Input Pins
I
The data inputted to these pins are fatched
at the end of the display cycle.
-
Logic Ground Pin
-
Logic Power Supply
High-Voltage Segment Output Pins
O
Also acts as the Key Source
-
Pull-Down Level
O
High Voltage Segment/Grid Output Pins
O
High-Voltage Grid Output Pins
Pin No.
1 to 4
5
6
7
8
9
10, 11
12, 44
13, 43
14 to 29
30
31 to 38
39 to 42
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