Toshiba SD-2550A Service Manual page 84

Table 3-5-4 TMP94C251AF(Z) (5/5)
Pin
Name
No.
142 ADVCC 10 bit AD converter power supply terminal
141 ADVSS 10 bit AD converter GND terminal (0V)
144 DAVCC 8 bit DA converter power supply terminal
143 DAVSS 8 bit DA converter GND terminal (0V)
36 CLVCC Power supply terminal for clock doubler.
34 CLVSS GND terminal for clock doubler.
5, DVCC Digital power supply terminal (+5V)
27,
43,
61,
78,
88,
98,
116
14, DVSS Digital GND terminal (0V)
37,
54,
69,
87,
89,
107,
130
Function
3-25
Table 3-5-5 ZR36732 (1/5)
Pin
Name
No.
Host interface, CD-DSP interface, sub code interface (32 pins)
124 RESET# Reset input (active: low). Initializing
process of the device will start when
deasserting is performed after asserting.
122 STDBY# Standby input (active: low). When asserting
in accordance with RESET#, all the output
pins and bidirectional pins enter the float
state, and the device is electrically cut off.
All internal operations stop and the power
consumption can be minimized. At standby,
contents of SDRAM and setup parameters
are not preserved.
160 IDLE Display output of Idle, Init or Reset state
(active high). After reset, the device enters
the active state.
2 HWID Determines the data bus width of host
interface. Only during reset, modification
will be available. At low level (GNDP), the
host interface of the device is set to 2 or 8
bit width, at high level (VDDP) is set to 16
bit width.
1 HORD Determines the bite order of host interface
data bus at 16 bit width (HWID is VDDP).
Only during reset, modification will be
available. Sets the device so that m.s. bite
is entered/developed by HD [15:8] at low
level (GNDP), and m.s. bite is done by HD
[7:0] at high level (VDDP).
Connects to GNDP when HWID is at GND
level.
4 HTYPE Determines protocol of the host bus. Only
during reset, modification will be available.
Sets the device to type A at low level
(GNDP) and type B at high level (VDDP).
20 HD[7:0] 8 l.s of the host data bus. When connecting
| (HD[7:4]) HWID input to GNDP, only the 8 l.s. signal
25, (HD[3]) is defined as a host data signal. When
17, (HD[2:1]) connecting HWID to VDDP, the connection
18 (HD[0]) is used as a 8 l.s. line of 16 bit data bus.
9, HD[11:8] When connecting HWID to VDDP, the
11, (HD[11]) connection is used as 11:8 data line of 16
13, (HD[10:8]) bit host data bus.
15
HD[15:12] When connecting HWID to VDDP, the
connection is used as 15:12 data line of 16
bit host data bus. When connecting HWID
to GNDP, the connection is used as CD-
DSP serial input port pin as defined below.
8 CDCLK CD-DSP bit clock input.
(HD[12])
7 CDDAT CD-DSP data input.
(HD[13])
6 CDFRM CD-DSP LR clock (Frame) input.
(HD[14])
5 CDERR CD-DSP data error input.
(HD[15])
27 HA[3:0] Host address input. Inputs address signal
| which specifies the physical address of the
30 device.
32 HCS# Host chip select input. Active: low.
31 HWR# (HR/ Host protocol type A (HTYPE=GNDP): HR/
W#) W#. The input to determine the direction of
host access.
Host protocol type B (HTYPE=VDDP):
HWR#. Host write input (Active: low).
34 HRD# Host protocol type A (HTYPE=GNDP):
(HDS#) HDS#. Data strobe input (Active: low).
Host protocol type B (HTYPE=VDDP):
HRD#. Host read in input (Active: low).
Function