Linear Technology 1317A-D Quick Start Manual page 5

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1317A-D
ACTIVE RESET ISOLATED 18-72V INPUT TO 24V @5A DC/DC POWER CONVERTER
remove the resistor R1 and connect 12V, 100mA
power source to +Vb node (right side of R1). By
doing this, the primary PWM controller LT1952 can
be activated without the main primary power being
applied to +Vin.
To activate the secondary side control circuit
LT4430 diode OR a 5V, 100mA power source into
pin 1 of LT4430 controller.
Once the primary and secondary controllers are
running the main power (+Vin) can be applied
slowly while observing the switching waveforms
and output voltage.
The input current supplying the power transformer
T1 should not exceeded 200mA without the output
load. If one of the MOSFETs is damaged, the input
current will exceed 200mA.
PCB LAYOUT
The PCB layout should be carefully planned to avoid
potential noise problems. The PCB layout for DC1317A
can be used as a guide. Since demo board DC1317A
has 8 versions the PCB layout has optional compo-
nents that can be removed. The schematic in figure 7
is showing the circuit without any optional compo-
nents. Also, the circuit in figure 7 does not show any
zero-ohm resistors. Please consult the schematic on
page 7 to determine if any of the options should be
included in your PCB layout.
Also, the PCB layout has a common schematic that is
used just for the layout. The PCB layout schematic is
not included in this quick start guide but it is included
with PCB design files.
Please note that the actual circuit schematic on page 7
shows the component values. The PCB layout sche-
matic included with design files does not show the
component values.
In some cases, a different component like a diode is
used in a place holder for a capacitor such as in the
case of C6. Please modify the reference designators in
your schematic to reflect the actual component used.
The following simple PCB layout rules should be help-
ful.
If possible use solid ground planes on layers 2 and
n-1. The ground planes will prevent the switching
noise from coupling into sensitive lines.
Place sensitive lines on the inner layers that will be
shielded by grounds on layers 2 and n-1.
Keep the loop formed by Q1, RCS1, Cin and T1 tight.
Keep the loop formed by Q2, Q3 and T1 tight.
Keep noise sensitive nodes like SD/VSEC, ROSC, FB,
COMP, ISENSE, BLANK and DELAY as small as posible
by placing the associated components close to the
LT1952 and LT4430 chips.
Use local vias for all components that connect to
ground planes.
Do not place any traces on the layers 2 and n-1 to
avoid ground planes from being compromised.
If the PCB layout has to be done on 2 or 4-layer PCB
try to stay close to the guidelines outlined above. Also,
maximize the ground connections between compo-
nents by placing the components tight together.
Please contact LT factory for additional assistance.
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