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xCORE-200 Clock Frequency Control
Register
XS1_SSWITCH_PLL_CTL_NUM
XS1_SSWITCH_PLL_CTL_NUM
XS1_SSWITCH_PLL_CTL_NUM
XS1_SSWITCH_PLL_CTL_NUM
XS1_SSWITCH_PLL_CTL_NUM
XS1_SSWITCH_CLK_DIVIDER_NUM
Figure 4:
XS1_SSWITCH_REF_CLK_DIVIDER_NUM
Node Config-
uration
Registers
Register
Figure 5:
XS1_PSWITCH_PLL_CLK_DIVIDER_NUM
Tile Configu-
ration control
registers
6.2 24MHz Oscillator
Use MODE[1:0] = 11, ie, leave any mode pins Not Connected. For the initial boot,
the system clock will be 100.0MHz, with the xCORE tile also running at 384 MHz.
The following are required: R = 0, F = 124, OD = 2. Write 0xC1007C00 to the PLL
Settings register in the Node Configuration to bring the PLL output up to 500MHz,
with code similar to the following:
# define PLL_500MHz 0 x01007C00
...
unsigned p l lC t rl Re a dD at a ;
r e a d _ n o d e _ c o n f i g _ r e g ( tile [0] , XS1_SSWITCH_PLL_CTL_NUM , pllCtrlRe adData ) ;
if ( pl l Ct r lR ea d Da ta != PLL_500MHz ) {
}
...
XM010761A
w r i t e _ n o d e _ c o n f i g _ r e g ( tile [0] , XS1_SSWITCH_PLL_CTL_NUM , PLL_500MHz ) ;
Bitfield
Reset
Description
[6:0]
Mode Pins R; PLL input divider stage =
R+1
[20:8]
Mode Pins F; Multiplier stage of the PLL
= (F+1)/2
[25:23] Mode Pins OD; PLL output divider stage
= OD+1
30
N/A
LOCKN; '0' will force a wait
for PLL lock
31
N/A
RESETN; '0' will force reset
on PLL change
[15:0]
0
System switch clock divider
= SSDIV+1. Reset value pro-
duces 400MHz for a 400MHz
system clock
[15:0]
3
Reference clock divider = REF-
DIV+1. Reset value produces
100MHz for a 400MHz sys-
tem clock.
Bitfield Reset Description
[15:0]
0
xCORE
XCDIV+1. Reset value produces
400MHz for an 400MHz system
clock
4/8
Tile
clock
divider
=
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