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xCORE-200 Clock Frequency Control
If a different PLL configuration is required from that used to boot the application,
the new settings should be written to the PLL_CTRL register. The PLL_CTRL register
comprises five fields (R, F, OD, LOCKN, RESETN), detailed in §5. That register
contains a bit to instruct the PLL to hold the chip in reset, and a bit to pause the
chip whilst the PLL is not locked.
Small changes to either R or F that result in a frequency change of no more than
+/- 20% can be made by writing a new value to the register with a '1' in the RESETN
bit and a '1' in the LOCKN bit (0xCnnn nnnn). The PLL will gradually adjust to the
new values without either the need for a reset or a lock.
Larger changes to R or F, or changes that require both R and F to be modified,
or changes to OD can be made by writing a '0' in the RESETN bit and a '0' in the
LOCKN bit (0x0nnn nnnn).
If you choose to reset the device (by setting the RESETN bit low), the boot code
should read the value of the PLL_CTRL register and compare it to the reconfigured
value. If there is a difference, then this is the first time the boot code has executed
and the new PLL settings should be written to PLL_CTRL, causing a reset. The
second time the boot code executes, the value read back from the PLL_CTRL
register will be the reconfigured value and the boot process can continue.
The easiest way to reprogram the PLL is to specify the application's frequency
requirements in the XN file and use the xTIMEcomposer tools to reprogram the
PLL—see §8.1.
5 Frequency Control Registers
To access the frequency control registers packets of data must be constructed
and communicated to the Switch through a channel end. Global PLL settings are
controlled through registers in the Node Configuration control registers. From C or
XC, use the write_node_config_reg() and read_node_config_reg() functions defined
in xs1.h. The bits that can be controlled are shown in Figure 4.
Settings on an individual tile basis are controlled through registers in the Tile
Configuration control registes. From C or XC, use the write_tile_config_reg() and
read_tile_config_reg() functions defined in xs1.h. The bits that can be controlled
are shown in Figure 5.
6 Example PLL Configurations
6.1 Standard Configuration: 25MHz Oscillator
Use MODE[1:0] = 11, ie, leave any mode pins Not Connected. The PLL will configure
to the standard 400MHz, with the xCORE tile and SSwitch running at 400MHz, with
a 100MHz reference clock.
XM010761A
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