Sony DCR-PC8E Service Manual page 9

COVER COVER
For Schematic Diagram
• Refer to page 4-65 for printed wiring board.
2
1
VC-265D BOARD(5/16)
DV INTERFACE(JC-2 BLOCK)
XX MARK:NO MOUNT
A
:Voltage measurment of the CSP IC
and the Transistors with mark,is
not possible.
MCDA7
MCDA7
MCDA6
MCDA6
MCDA5
MCDA5
B
MCDA4
MCDA4
MCDA3
MCDA3
MCDA2
MCDA2
47
(4/16,
MCDA1
10/16)
MCDA1
MCDA0
MCDA0
MCCE
MCCE
RDX
RDX
WRX
WRX
C
ALE
ALE
TRCK
LCKO
FCLR
FCLR
FRL
FRL
49 XENA
XENA
(4/16)
LBUS0
D
LBUS0
LBUS1
LBUS1
LBUS2
LBUS2
LBUS3
LBUS3
XACC
XACC
DIR
DIR
XRST_LINK
XRST_LINK
XDVCN
XDVCN
E
XRST_PHY
XRST_PHY
59
(10/16) LIP_SLEEP
LIP_SLEEP
LPS
LPS
OFR
OFR
FB5601
0uH
D_1.9V
F
D_2.8V
60
(15/16)
FB5602
0uH
C5601
0.1u
B
REG_GND
16
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4-2. SCHEMATIC DIAGRAMS
4-2. SCHEMATIC DIAGRAMS
3 4 5
40 39 38 37
VDD2
LBUS3
ID3
LBUS2
ID2
LBUS1
ID1
LBUS0
ID0
VSS
ICLK
VSS
XENA
XINEN
FRL
FR
OFR
OFR
FCLR
IFCLEAR
VDD3
TEST0
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
LPS
LCKO
L5601
10uH
C5608
C5609 C5613
10u
0.01u 0.01u
6.3V
B B
C5607
0.01u
B
4-27
VC-265D BOARD SIDE A VC-265D BOARD SIDE B
VC-265D BOARD SIDE A VC-265D BOARD SIDE B
6 7 8
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VSS
CNA
XRESETP
PWD
VDD3
VDD2
AVS
IC5603
AVD3
AVD3
DV INTERFACE
R1
IC5603
SN104266GGM-BG
R0
CSP(CHIP SIZE PACKAGE)IC
TPA+
TPA-
TPB+
TPB-
AVD3
TPBIAS
AVS
AVD3
AVS
C5614
0.1u
B
9 10
XDVCN
XRST_PHY
SIGNAL PATH
LIP_SLEEP
VIDEO SIGNAL
CHROMA Y
REC
R5752 R5755
12k
12k
± 0.5% ± 0.5%
PB
R5758 R5761
R5759
56 56
± 0.5% ± 0.5%
C5616 R5760 R5762
1u
10k
± 0.5%
B
4-28
DCR-PC8E
11 12
AUDIO
Y/CHROMA SIGNAL
TPA+
TPA-
61
(16/16
(CN012))
TPB+
TPB-
R5763
56 56
± 0.5% ± 0.5%
C5617
10k 220p
± 0.5%
CH
VC-265D (5/16)