Marantz SR7300 Service Manual page 32

QC01 : NJU3430FG1
R ST
RESET
Inst ruct ion
Decode r
SI
CS 8bits
Shift
CL K
Re g.
R S
Timing State
Ge n.
OSC
1 C R Display
OSC.
OSC
2
V
D D
V
SS
V
FDP
N o . S Y M B O L I/O
5 7 V
D D
4 9 V
S S
4 8 V
F D P
5 0 O S C
1
5 1 O S C O
2
5 4 C L K
5 3 C S
5 5 S I
5 6 R S
5 2 R S T
6 1 t o 6 4 ,
S to S O
1 3 5
1 t o 3 1
3 2 t o 4 7 T to T O
1 1 6
6 0 M K
1
O
5 9 M K
2
5 8 P O
1
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Line
Ad dress
Cou nter
Ad dress
Reg. Selector
Read
Ad dress
Cont ro l
Cou nter
F U N C T I O N
- P o w e r S o u r c e
- G N D
V F D D r i v i n g P o w e r S o u r s e
-
V - 2 0 V t o V - 4 5 V
D D D D
C R O s c i l l a t i o n T e r m i n a l
I
External R and C connect to these terminals.
(Target f = 3 6 0 k H z )
O S C
Serial Clock Input Terminal
I The serial data input synchronizing the rise edge of this
terminal.
C h i p S e l e c t T e r m i n a l
I W h e n t h e C S t e r m i n a l i s " H " t h e s e r i a l d a t a i n p u t i s n o t
a v a i l a b l e .
S e r i a l D a t a I n p u t T e r m i n a l
I
The data input is MSB first.
Register Selection Signal Input Terminal
I RS="0" : Instruction Register
R S = " 1 " : D a t a R e g i s t e r
R e s e t T e r m i n a l R S T = " L " : R e s e t
- E a c h A d d r e s s
- E a c h R A M D a t a
I
- D i s p l a y D i g i t s
- C o n t r a s t C o n t r o l
-All Display Off
-All Outputs are "L"
Segment Output Terminals (Internal Pull-down
R e s i s t a n c e )
Timing Output Terminals (Internal Pull-down Resistance)
Icon Output Terminals (Internal Pull-down Resistance)
Output Port Terminal
T h i s t e r m i n a l i s s u i t a b l e f o r L E D .
MK RAM Icon
16x2 bit Dr ive r
CG RAM Segment
35x8 bit Dr ive r
Port
Dr ive r
CG ROM
8,4 00 b it
DD RA M
16x8 bit
Timing
Dr ive r
: V = + 3 . 0 t o 5 . 5 V
D D
: V = 0 V
S S
: (00)
H
: Unfixed
: 1 6 - d i g i t
: 8/16 Dury
44
MK MK
1 ~ 2
S S
~
1 35
P
1
T ~ T
1 1 6