Marantz SR7300 Service Manual page 27

Q600 : CS494001-CQ
99 MCLK Audio Master Clock
100 VDD2 2.5V Supply Voltage
101 VSS2 2.5V Ground
102 I/O AUDATA4, Digital Audio Output 4, General Purpose I/O
GPIO28
103 I/O HDATA4, DSP C Bidirectional Data Bus, General Purpose I/O
GPIO4
104 O SCLK0 Audio Output Bit Clock
105 I/O HDATA3, DSP C Bidirectional Data Bus, General Purpose I/O
GPIO3
106 O AUDATA3, Digital Audio Output 3, S/PDIF Transmitter
XMT958A
107 O AUDATA2 Digital Audio Output 2
108 O LRCLK0 Audio Output Sample Rate Clock
109 O AUDATA1 Digital Audio Output 1
110 O AUDATA0 Digital Audio Output 0
111 I CMPCLK, PCM Audio Input Bit Clock
FSCLKN2
112 I/O HDATA2, DSP C Bidirectional Data Bus, General Purpose I/O
GPIO2
113 VSS3 2.5V Ground
114 VDD3 2.5V Supply Voltage
115 I/O HDATA1, DSP C Bidirectional Data Bus, General Purpose I/O
GPIO1
116 I/O HDATA0, DSP C Bidirectional Data Bus, General Purpose I/O
GPIO0
117 O CMPREQ, Frame Clock Data Request Out
FLRCLKN2
118 I CMPDAT, PCM Audio Data Input Number Two
FSDATAN2
119 I FLRCLKN1 PCM Audio Input Sample Rate Clock
120 I/O WR, DS, Host Write Strobe, Host Data Strobe, General Purpose I/O
GPIO10
121 I/O RD, R/W, Host Parallel Output Enable, Host Parallel R/W, General
GPIO11 Purpose I/O
122 PLLVSS PLL Ground Voltage
123 FILT2 Phase Locked Loop Filter
124 FILT1 Phase-Locked Loop Filter
125 PLLVDD PLL Supply Voltage
126 O CLKOUT, Crystal Oscillator Output
XTALO
127 I CLKIN, XTALI External Clock Input/Crystal Oscillator Input
128 CLKSEL DSP Clock Select
129 I/O CS, GPIO9 Host Parallel Chip Select, General Purpose I/O
130 I/O A0, GPIO13 Host Parallel Address Bit 0, General Purpose I/O
131 I FSDATAN1 PCM Audio Data Input One
132 VDD4 2.5V Supply Voltage
133 VSS4 2.5V Ground
134 I FSCLKN1, PCM Audio Input Bit Clock
STCCLK2
135 SCS Host Serial SPI Chip Select
136 I SCDIN SPI Serial Control Data Input
137 VSS5 2.5V Ground
138 VDD5 2.5V Supply Voltage
139 I/O A1, GPIO12 Host Address Bit 1, General Purpose I/O
140 I/O SCDOUT, Serial Control Port Data Input and Output
SCDIO
141 I/O HINBSY, Input Host Message Status, General Purpose I/O
GPIO8
142 SCCLK Serial Control Port Clock
143 I/O UHS2, Mode Select Bit 2, External Serial Memory Chip Select,
CS_OUT, General Purpose I/O
GPIO17
144 I RESET Master Reset Input
Q901 : LC72722
Pin Assignment
V REF 1 24 SYR
MPXIN 2 23 CE
Vdda 3 22 DI
Vssa 4 21 CL
FLOUT 5 20 DO
LC72722
CIN 6 19 RDS-ID
LC72722M
T1 7 18 SYNC
LC72722PM
T2 8 17 T7(CORREC/ARI-ID/TA/BEO)
T3(RDCL) 9 16 T6(ERROR/57K/TP/BE1)
T4(RDDA) 10 15 Vssd
T5(RSFT) 11 14 Vddd
X OUT 12 13 X IN
Top view
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Block Diagram
+5V
Vdda
REFERENCE
VOLTAGE
Vssa
MPXIN ANTIALIASING
FILTER
DO
CL
CCB
DI
CE
T1
TEST
T2
T3 to T7
39
Q901 : LC72722
Pin Functions
Pin No. Pin name I/O
1 VREF Output Reference voltage output (Vdda/2)
2 MPXIN Input Baseband (multiplexed) signal input
5 FLOUT Output Subcarrier output (filter output)
6 CIN Input Subcarrier input (comparator input)
3 Vdda — Analog system power supply (+5 V)
4 Vssa — Analog system ground
12 XOUT Output Crystal oscillator output (4.332/8.664 MHz)
13 XIN Input Crystal oscillator input (external reference signal input)
7 T1 Input Test input (This pin must always be connected to ground.)
Test input (standby control)
8 T2 Input
0: Normal operation, 1: Standby state (crystal oscillator stopped)
9 T3 (RDCL) Test I/O (RDS clock output)
I/O*
10 T4 (RDDA) Test I/O (RDS data output)
I/O*
11 T5 (RSFT) I/O* Test I/O (soft-decision control data output)
Test I/O (error status output, regenerated carrier output,
T6 (ERROR/
16 I/O*
TP output, error block count output)
57K/TP/BE1)
T7 (CORREC/ Test I/O (Error correction status output, SK detection output,
17 I/O*
TA output, error block count output)
ARI-ID/TA/BE0)
18 SYNC I/O* Block synchronization detection output
19 RDS-ID Output RDS detection output
20 DO Output Data output
21 CL Input Clock input
22 DI Input Data input
23 CE Input Chip enable
24 SYR Input Synchronization and RAM address reset (active high)
14 Vddd — Digital system power supply (+5 V)
15 Vssd — Digital system ground
Note: * Normally function as an output pin. Used as an I/O pin in test mode,
which is not available to user applications.
V REF
FLOUT CIN
+
PLL
(57 kHz)
–
V REF
57 kHz
BPF
SMOOTHING
(SCF)
FILTER
RAM ERROR CORRECTION
(24 BLOCK DATA) (SOFT DECISION)
CLK(4.332 MHz)
MEMORY CONTROL
OSC/DIVIDER
X IN X OUT
Function
Serial data interface (CCB)
+5V
Vddd
CLOCK
RECOVERY
(1187.5 Hz)
Vssd
DATA
RDS-ID
DECODER
SYNC
SYNC/EC CONTROLLER
SYR
SYNC SYNC
DETECT-1 DETECT-2