Marantz SR7300 Service Manual page 25

QK30 : CS5361-KSR
RST 1 24
M/S 2 23
LRCK 3 22
SCLK 4 21
5 20
MCLK
VD 6 19
GND 7 18
VL 8 17
SDOUT 9 16
10 15
DIV
11 14
HPF
DIF 12 13
I/O
Pin Name # Pin Description
RST I 1 Reset ( Input ) - The device enters a low power mode when low.
M/S I 2 Master/Slave Mode (Input) -In Slave mode, LRCK and SCLK become input. (FIXED LOW)
LRCK I 3 Left Right Clock ( Input ) - Determines which channel, Left or Right, is currently active on the
serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
SCLK Serial Clock ( Input ) - Serial clock for the serial audio interface.
I 4
MCLK I 5 Master Clock ( Input ) - Clock source for the delta-sigma modulator and digital filters. Table 1 illustrates
several standard audio sample rates and the required master clock frequency.
VD I 6
Digital Power ( Input ) - Positive power supply for the digital section. Refer to the Recommended Operat-
ing Conditions for appropriate voltages.
GND I 7,18 Ground ( Input ) - Ground reference. Must be connected to analog ground.
VL I 8 Logic Power ( Input ) - Determines the required signal level for the digital input/output. Refer to the Rec-
ommended Operating Conditions for appropriate voltages.
SDOUT O 9 Serial Audio Data Output ( Output ) - Output for two's complement serial audio data.
DIV I 10 MCLK Divider (Input ) - (FIXED LOW)
HPF I 11 High Pass Filter Enable (Input ) - The device includes a high pass filter after the decimator to remove
the indeterminate DC offsets introduced by the analog buffer stage and the analog modulator. The first-
order high pass filter response characteristics are detailed in the Digital Filter specifications table. The fil-
ter response scales linearly with sample rate.
DIF I 12 Digital Interface Format ( Input ) - The required relationship between the Left/Right clock, serial clock
and serial data is defined by the Digital Interface Format selection. Refer to Figures 8 and 9.
M0 I 13, Mode Selection ( Input ) -(FIXED LOW)
M1
I 14
(FIXED LOW)
TST Test Pin (Input) - This pin needs to be connected to GND.
I 15
AINL+ I 16, Differential Left Channel Analog Input ( Input ) - Signals are presented differentially to the delta-sigma
AINL- modulators via the AINL+/- pins. The full scale differential analog input level is specified in the Analog
I 17
Characteristics Specification table.
19
VA I Analog Power ( Input ) - Positive power supply for the analog section. Refer to the Recommended Oper-
ating Conditions for appropriate voltages.
AINR+ I 20, Differential Right Channel Analog Input ( Input ) -Signals are presented differentially to the delta-sigma
AINR- modulators via the AINR+/- pins. The full scale differential analog input level is specified in the Analog
I 21
Characteristics Specification table.
VCOM O 22 Common Mode Voltage (Output) - Nominally 2.5 volts; can be used to bias the analog input circuitry to
the common mode voltage of the CS5361. VCOM is not buffered and the maximum current is 10 uA.
I 23 Reference Ground ( Input ) - Ground reference for the internal sampling circuits and must be connected
REF_GND
to analog ground.
Positive Voltage Reference ( Output ) - Positive reference voltage for the internal sampling circuits.
FILT+ O 24
Requires the capacitive decoupling to GND as shown in the Typical Connection Diagram.
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V C O M
FILT+
REFGND
F ILT + Volta ge R e fe ren ce
VCOM
AINR+
A IN L-
+
AINR-
A IN L+
-
VA
S /H
GND
AINL-
AINL+
A IN R -
+
TST
A IN R +
-
S /H
M1
M0
37
V S C L K
R E F G N D L R C K
L
S e rial O utpu t Interfa ce
D igital
LP Filter Q
D e cim ation
F ilte r
D A C
D igital
LP F ilter Q
D e cim ation
F ilte r
D A C
S D O U T M C LK
R S T
D IF
M /S
H PF
H ig h
P a ss
D IV
F ilter
H ig h
M O D E 0
P a ss
F ilter M O D E 1