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Schematic Diagram page
3
/28
FANVCC
FANVCC
002:8D
002:5D
G4
004:2E
005:1C
006:1A
D+3.3V
DZ01
009:1A
1SS355
011:1A
1
2
016:1A
D+3.3V
017:1A
017:6C
019:3E
019:4A
019:4D
019:6A
019:6D
020:4E
• Since this is a basic circuit diagram, the value of the parts is subject to be altered for improvement.
3
4
FANVCC
AMP_PWR
A x R2/(R1+R2) -(0.2~0.8)
G2
> 2.8〜3.1V
G1
13.0〜16.9V protect
GND(FAN)
3
To FAN1
FANLOCK
2
FANVCC
1
Tcon+12V
PZ01
GH-03H
GND1
A x R2/(R1+R2) -(0.2~0.8)
> 2.8〜3.1V
13.0〜16.9V protect
+5.6V
A x R2/(R1+R2) -(0.2~0.8)
FAN_ALRM
> 2.8〜3.1V
009:1B
7.4〜9.6V protect
D+3.3V
A x R2/(R1+R2) -(0.2~0.8)
> 2.8〜3.1V
4.1〜5.34V protect
5
RZ03
10k-1%
DZ04
1SS355
1
2
RZ04
1.8k-1%
GND1
AMP_PWR
002:5E
AMP_PWR
020:2B
RZ05
10k-1%
DZ05
1SS355
1
2
RZ06
3.0k-1%
GND1
2.8V Detect ±2%
ΔTH 0.084V〜0.224V
・ 2.8V〜3.1V detect
Tcon+12V
002:8C
Tcon+12V
019:6C
RZ07
DZ10
10k-1%
DZ06
UDZS5.6B
1SS355
1
2
RZ08
GND1
3.0k-1%
GND1
002:5C
004:2A
+5.6V
008:4A
009:1C
011:1B
+5.6V
012:1A
015:2A
RZ09
016:1A
10k-1%
DZ07
1SS355
020:2B
1
2
RZ10
6.8k-1%
GND1
002:5D
C6
004:2E
005:1C
006:1A
D+3.3V
009:1A
011:1A
016:1A
D+3.3V
017:1A
017:6C
RZ11
019:3E
10k-1%
DZ08
019:4A
1SS355
1
2
019:4D
019:6A
019:6D
RZ12
020:4E
27k-1%
GND1
62
6
7
OVDET_N
012:1E
RZ21
2
10k
1
2
3
QZ01
1
2SC5383-T111-1F
RZ20
RZ22
470k
47k
CZ01
0.1/16
1005
GND1
GND1
IZ01
9/28 Change IZ01
PST8328NR
Richo -> PST8328NR
CZ02
10/11 Change CZ02
3300p
1005
GND1
ResetIC Delay Time
t(s) = 0.69 x Rd x Cd
= 0.69 x 10x10^6 x C(F)
= 6.9 x10^-6 x C (pF)
t(ms) = 6.9 x10^-3 x 3300
= 6.9 x 3.3
= 23 ms
OVP
━━
MAIN BOARD SHEET: 003
Initial Release
Folder Path
D8MW
A
B
C
D
E
F
Fan power, OVP
/DG-DAT/FPD/D8M/D8M-Main/
D8M-Main-47-B2B_001/D8M-
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