Aiwa XD-DV300 Service Manual page 34

Pin No. Pin Name
123 VSS
124-126 SBD_12-10
127 VDD
128, 129 SBD_9, 8
130 SCLK
131 VSS
132-134 SBA_9-7
135 VDD
136-138 SBA_6-4
139 VSS
140-142 SBA_3-1
143 VDD
144 SBA_0
145, 146 SBA_10, 11
147 VSS
148 SCS1_N
149 SCS_N
150 SRAS_N
151 VDD
152 SCAS_N
153 SWE_N
154 SDQM
155 VSS
166 PLLVDD
157 NC
158 PLLVSS
159 VDD
160 NC
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I/O
I Ground.
I/O SDRAM data bus 12-10.
I Power (3.3V).
I/O SDRAM data bus 9, 8.
I/O SDRAM 81MHz clock.
I Ground.
O SDRAM address bus 9-7.
I Power (3.3V).
O SDRAM address bus 6-4.
I Ground.
O SDRAM address bus 3-1.
I Power (3.3V).
O SDRAM address bus 0.
O SDRAM address bus 10, 11.
I Ground.
O Chip select for second DRAM.
O Chip select for SDRAM.
O SDRAM row address strobe.
I Power (3.3V).
O SDRAM column address strobe.
O SDRAM write enable.
O SDRAM control pin.
I Ground.
I Power-phase locked loop for SDRAM.
— Not connected.
I Phase locked-loop ground pin.
I Power (3.3V).
— Not connected.
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Description