Aiwa XD-DV300 Service Manual page 33

All manuals and user guides at all-guides.com
Pin No. Pin Name
71 VDD
72 OSD_ACTIVE
73, 74 PD_0, 1
75 VSS
76-78 PD_2-4
79 VDD
80 NC
81 VSS
82-84 PD_5-7
85 VSS
86 BLANK
87 CREF
88-91 EXT_OSD_0-3
92 NC
93 VDD
94 ACLK_441
95 ACLK_48
96 ACLK_32
97 VSS
98 CD_BCLK
99 CD_LRCLK
100 CD_ACLK
101 CD_ASDATA
102 SPDIF_IN
103 A_ACLK
104 VDD
105 BCLK
106 LRCLK
107 ASDATA
108, 109 NC
110 VSS
111 SPDIF_OUT
112 AUDIO_SYNC
113, 114 TM1, TM0
115 ZTEST
116 SCAN_TE
117 PREQ_N
118 VDD
119, 120 SBD_15, 14
121 NC
122 SBD_13
I/O
I Power (3.3V).
O On screen display active.
O Pixel data output bus 0, 1.
I Ground.
O Pixel data output bus 2-4.
I Power (3.3V).
— Not connected.
I Ground.
O Pixel data output bus 5-7.
I Ground.
O Blank (composite).
O Chroma reference for pixel data.
I External OSD palette selection bus 0-3.
O Not connected.
I Power (3.3V).
I Audio input clock for 44.1kHz*N.
I Audio input clock for 48kHz*N.
I Audio input clock for 32kHz*N.
I Ground.
I CD-Serial DAC bit clock.
I CD-Left right clock.
I CD-External audio clock.
I CD-Audio serial data line.
I Sony/Philips data interface-input.
O Output audio clock.
I Power (3.3V).
O Serial DAC bit clock.
O Serial DAC left right clock.
O Audio serial data line.
O Not connected.
I Ground.
O Sony/Philips data interface output.
O Audio sync strobe.
I Test mode 1, 0.
I Test mode pin.
I Scan test mode pin.
O PCM FIFO request.
I Power (3.3V).
I/O SDRAM data bus 15, 14.
— Not connected.
I/O SDRAM data bus 13.
47
Description