Asus AAEON GENE-BT05 User Manual page 14

Appendix A - Watchdog Timer Programming ................................................................... 99
A.1 Watchdog Timer Registers ................................................................................ 100
A.2 Watchdog Sample Program ............................................................................... 101
Appendix B - I/O Information ............................................................................................. 104
B.1 I/O Address Map ................................................................................................. 105
B.2 Memory Address Map ....................................................................................... 106
B.3 IRQ Mapping Chart ............................................................................................. 107
B.4 DMA Channel Assignments ............................................................................... 110
Appendix C - Mating Connectors ....................................................................................... 111
C.1 List of Mating Connectors and Cables ............................................................. 112
Appendix D - Electrical Specifications for I/O Ports ......................................................... 114
D.1 Electrical Specifications for I/O Ports ................................................................ 115
Preface XIV