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4.7
DVMAIN SCHEMATIC DIAGRAM
MAIN (DVMAIN)
0
1
TO
MAIN IF
CN107
TDO
TMS
TO MAIN IF
TCMK
CN107
TRST
R3059
100
TO DSP
TDA
5
C3047
TO
MAIN IF
CN109
L3002
DIGITAL_3V
D_REG3V
NQR0129-002X
TO DSP
REG_2.5V
REG_1.8V
TO MAIN IF
C3003
NCB30JK-105X
A_REG3V
1
CN109
GND
L3003
DIGITAL_2.5V
NQR0129-002X
C3004
NCB30JK-105X
1
L3005
DIGITAL_1.8V
NQR0006-001X
C3007
NCB10JK-106X
10
L3004
4
ANALOG_2.5V
NQR0006-001X
C3005
NBE20JM-106X
10
/6.3
T
L3006
ANALOG_1.8V
NQR0006-001X
C3008
NBE20JM-106X
10
/6.3
T
L3001
D3004
MA2Z720-X
PHY_2.85V
NQR0129-002X
Q3001
∗
C3001
10
/6.3
T
R3061
∗
R3062
∗
R3063
∗
Q3002
∗
3
L3012
∗
R3052
∗
R3054
C3010
∗
T
C3006
C3009
∗
∗
2
TO
MAIN IF
CN106
AGC_OUT
VRB_AGC
VREF_1.1
REC_DATA
REC_CLK
REC_CTL
REF_CLK
ATFI
VRB_ATF
L3015
NQR0006-001X
R3046
R3045
C3056
∗
T
1
∗
∗
NOTE : The parts with marked ( ) is not used.
A
B
C3041
C3040
0.01
0.01
N.C
N.C
∗
MON0
MON1
VDDE
VDDI
MON2
MON3
MON4
MON5
VSS
MON6
MON7
MON8
MON9
MON10
C3042
MON11
0.01
MON12
C3043
VDDE
VDDI
0.01
MON13
MON14
MON15
MON16
MON17
MON18
MON19
VSS
MON20
MON21
MON22
MON23
VDDE
MON24
MON25
MON26
MON27
VDDE
C3044
0.1
N.C
VDDP
VSSP
VDDA
VSS
N.C
N.C
VDDE
VSS
VSS
VDDE
VDDI
VSS
VDDE
VDDE
VDDI
VSS
VSS
MTEST
C3045
0.1
PHYAVD2
BUSRST
10k
PHYAVS2
R3053
PMODE
10k
PWR3
10k
PWR1
PWR2
R3055
VDDI
10k
PHYAVS1
PHYAVD3
C3046
0.01
PHYAVD1
VSS
VDDE
A/D
VCO
D/A
D/A
VDDI
VSS
C3011
0.1
∗
R3050
R3003
1M
C3014
C3054
1
0.01
82k
∗
R3040
2.2k
SN74AHC1G04K-X
IC3004
12k
VCO
R3043
IC3007
1.5k
JCY0174-X
R3041
R3044
560
∗
∗
C3067
2.7k
∗
C3052
0.047
C
NOTES :
For the destination of each signal and further line connections that are cut off from
this diagram , refer to "4.1 BOARD INTERCONNECTIONS".
When ordering parts , be sure to order according to the Part Number indicated in the Parts List.
CPUBUSTYPE
CPUDSLOGIC
CPUWAITLOGIC
CPUWAIT
XCPUCS
XCPURW
XCPUDSTB1
XCPUDSTB0
CPUALE
BRSI1
BRSI0
BRSO3
BRSO2
BRSO1
BRSO0
IC3001
AODAT0
AODAT1
AOBCK
AOLRCK
JCY0176
DODAT
DOBCK
DOLRCK
AIDAT0
AIDAT1
AIMCK
[DVMAIN]
AIBCK
AILRCK
DIMCK
DIBCK
DILRCK
OSC11O
OSC11I
OSC24O
OSC24I
VCXO12O
VCXO12I
VCXO11O
VCXO11I
VCIAUD
VCO
PWMAUDIO
LPFOUT
PHYAVS3
PHYVSR
PHYVSA
A/D
PHYVDR
PHYVDA
L3007
2.2µ
CH
R3009
10k
R3010
10k
TL3001
∗
C3062
TL3003
L3014
∗
10µ
IC3002
R3047
BU2501FV-X
1M
X3001
∗
R3068
R3048
[12ch_EVR_DAC]
∗
[41.85M]
220
∗
C3068
NAX0169-001X
0ohm
CH
CH
C3057
C3058
10p
9p
C3069
T
∗
D
E
4-15
4-16
XINT
INV
INH
OUTV
OUTH
BRSI3
BRSI2
YSI3
YSI2
YSI1
YSI0
YSO3
YSO2
YSO1
YSO0
VSS
C3038
0.1
VDDI
DIDAT
R3034
C3037
6P
2.2k
X3002
[NAX0480-001X]
C3036
6P
R3033
0Ω
L3008
L3009
∗
12µ
C3031
0.1
VDDP
C3030
0.1
CH
CH
C3032
C3033
C3034
C3035
∗
∗
0.001
12p
VSSP
VDDE
R3027
VSS
10k
VDDE
N.C
C3049
0.01
LPFIN
R3029
8.2k
R3036
R3037
C3048
VDDE
5.6K
560
0.22
C3029
0.01
C3050
0.01
CH
R3021
R3022
R3023
R3024
y10235001a_rev0.1
F
INV
TO VIDEO I/O, DSP
INH
R3005
10
TO MSD-CPU, DSP
OUTV
R3006
10
OUTH
TO DSP
DCO3
DCO2
DCO1
TO
DCO0
VIDEO I/O
DYO3
DSP
DYO2
DYO1
DYO0
DCI3
RA3001
DCI2
10
DCI1
DCI0
DYI3
TO DSP
RA3002
DYI2
10
DYI1
DYI0
CLK27A
TO
AUDIO AD/DA
RA3003
AODAT
AIDAT
AIMCK
AIBCK
AILRCK
10
TO
MSD-CPU
ADDT15
ADDT14
ADDT13
ADDT12
ADDT11
ADDT10
ADDT09
ADDT08
ADDT07
ADDT06
ADDT05
ADDT04
ADDT03
ADDT02
ADDT01
ADDT00
DV_WAIT
DRWSEL
DRE
DWE
DALE
DV_RST
CLK27SEL
SRV_TRK
TSR
FRP
SPA
TO MSD-CPU
HID1
TO
MAIN IF
CN107
SPA
FS_PLL
MAIN_VCO
PB_CLK
DISCRI
SBE
J101
0Ω
TPA+
0Ω
TPA-
0Ω
DV I/O
TPB+
0Ω
TPB-
L3010
∗
L3011
∗
AGC_GAIN
TO
NOSIG_LV
MAIN IF
ATF_GAIN
CN106
RECCADJ
DATA_OUT
TO
CLK_OUT
SYSCON-CPU
DAC_CS
H_OFFSET
TO
OP DRIVE
H_GAIN
G
H
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