Texas Instruments CC112 Series User Manual
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Texas Instruments CC112 Series User Manual

Low-power high performance sub-1 ghz rf transceivers/transmitter
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CC112X/CC1175
CC112X/CC1175 Low-Power High Performance
Sub-1 GHz RF Transceivers/Transmitter
User's Guide
SWRU295C
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Summary of Contents for Texas Instruments CC112 Series

  • Page 1 CC112X/CC1175 CC112X/CC1175 Low-Power High Performance Sub-1 GHz RF Transceivers/Transmitter User’s Guide SWRU295C Page 1 of 108...

  • Page 2: Abbreviations

    CC112X/CC1175 Abbreviations Abbreviations used in this data sheet are described below. 2-FSK Binary Frequency Shift Keying Least Significant Bit 4-FSK Quaternary Frequency Shift Keying Link Quality Indicator Adjacent Channel Power Microcontroller Unit Analog to Digital Converter Most Significant Bit Automatic Frequency Compensation Minimum Shift Keying Automatic Gain Control On-Off Keying...

  • Page 3: Table Of Contents

    CC112X/CC1175 Table of Contents ABBREVIATIONS ............................... 2 TABLE OF CONTENTS ............................. 3 OVERVIEW .............................. 5 CONFIGURATION SOFTWARE ......................6 MICROCONTROLLER INTERFACE ....................7 ............................7 ONFIGURATION SPI A ............................ 10 CCESS YPES PIN CTRL R ..................18 PTIONAL ADIO ONTROL EATURE ..................
  • Page 4 CC112X/CC1175 ........................67 ONTINUOUS RANSMISSIONS ......................... 67 ATTERY PERATED YSTEMS REGISTER DESCRIPTION ......................... 68 SOLDERING INFORMATION ......................106 DEVELOPMENT KIT ORDERING INFORMATION ..............106 REFERENCES ............................. 107 GENERAL INFORMATION ......................108 14.1 ..........................108 OCUMENT ISTORY SWRU295C Page 4 of 108...

  • Page 5: Overview

    CC112X/CC1175 CC1175 CC1120 is a transmitter based on the transceiver. This means that all TX CC1175 features/parameters described in this document are valid for the Overview CC112X is a family of high performance low power RF transceivers designed for operation with a companion MCU.

  • Page 6: Configuration Software

    CC112X/CC1175 SLEEP SPWD or wake-on-radio (WOR) SIDLE Lowest power mode. Most register values are retained Default state when the radio is not (see Table 5 for details ). receiving or transmitting. CSn = 0 IDLE SXOFF SCAL Used for calibrating frequency CSn = 0 synthesizer upfront (entering All register values are...

  • Page 7: Microcontroller Interface

    CC112X/CC1175 Microcontroller Interface Configuration CC112X In a typical system, will interface to an MCU. This MCU must be able to communicate with the CC112X over a 4-wire SPI interface to be able to: CC112X Configure the CC112X Program into different modes (RX, TX, SLEEP, IDLE, etc) Read and write buffered data (RX FIFO and TX FIFO) Read status information 3.1.1...
  • Page 8 CC112X/CC1175 Parameter Description Units SCLK frequency read/write access = 40 MHz SCLK XOSC Note: 100 or 125 ns delay between consecutive data bytes must be added during burst write access to the configuration = 32 MHz XOSC registers depending on f (40 or 32 MHz) XOSC SCLK frequency read access extended...
  • Page 9 CC112X/CC1175 Bits Name Description CHIP_RDYn Stays high until power and crystal have stabilized. Should always be low when using the SPI interface. STATE[2:0] Indicates the current main state machine mode Value State MARC State Description IDLE IDLE IDLE state Receive mode RX_END Transmit mode TX_END...

  • Page 10: Spi Access Types

    CC112X/CC1175 SPI Access Types Figure 4 shows the SPI memory map and the following sections are going to explain how the different SPI access types (see Table 3) should be used. Table 4 shows the SPI address space. 0x00 Register space 0x00 0x2E Extended register space...
  • Page 11 CC112X/CC1175 Access type Command/Address byte Description Burst Register Access Command: R/W ¯ 1 1 0 1 1 1 1 This access mode starts with a specific command (extended register space) Address: A (0x2F) The first byte following this command is interpreted as the extended address : See Table 5) 7 - 0...
  • Page 12 CC112X/CC1175 Write Read Single Byte Burst Single Byte Burst +0x00 +0x40 +0x80 +0xC0 0x00 IOCFG3 0x01 IOCFG2 0x02 IOCFG1 0x03 IOCFG0 0x04 SYNC3 0x05 SYNC2 0x06 SYNC1 0x07 SYNC0 0x08 SYNC_CFG1 0x09 SYNC_CFG0 0x0A DEVIATION_M 0x0B MODCFG_DEV_E 0x0C DCFILT_CFG 0x0D PREAMBLE_CFG1 0x0E PREAMBLE_CFG0...
  • Page 13 CC112X/CC1175 3.2.1 Register Space Access and Extended Register Space Access CC112X The configuration registers on the are located on SPI addresses from 0x00 to 0x2E (register space) with address extension command at address 0x2F to access the extended register space (see Figure 4).
  • Page 14 CC112X/CC1175 Extended Register Space (0x6F - 0x8C) Retention Extended Register Space (0x8D - 0xD9) Retention 0x6F IQIE_Q1 0x8D FSCAL_CTRL 0x70 IQIE_Q0 0x8E PHASE_ADJUST 0x71 RSSI1 0x8F PARTNUMBER 0x72 RSSI0 0x90 PARTVERSION 0x73 MARCSTATE 0x91 SERIAL_STATUS 0x74 LQI_VAL 0x92 RX_STATUS 0x75 PQT_SYNC_ERR 0x93 TX_STATUS...
  • Page 15 CC112X/CC1175 Address Strobe Description Name 0x30 SRES Reset chip Enable and calibrate frequency synthesizer (if SETTLING_CFG.FS_AUTOCAL = 1). 0x31 SFSTXON If in RX and PKT_CFG2.CCA_MODE ≠ 0: Go to a wait state where only the synthesizer is running (for quick RX/TX turnaround). 0x32 SXOFF Enter XOFF state when CSn is de-asserted...
  • Page 16 CC112X/CC1175 Both FIFO data and pointers are readable and writeable to enable e.g. re-transmissions, partial flush, partial readouts, changing only the sequence number before re-transmission etc. Figure 6 shows how the TX FIFO pointer changes as the FIFO is written and as data are sent on the air (assume variable packet length mode PKT_CFG0.LENGTH_CONFIG = 01b.
  • Page 17 CC112X/CC1175 NUM_RXBYTES = 0x00 126 127 RXFIRST RXLAST transmitted on the air and received by the radio NUM_RXBYTES = 0x04 126 127 RXFIRST RXLAST transmitted on the air and received by the radio NUM_RXBYTES = 0x08 126 127 RXFIRST RXLAST Figure 7: FIFO Pointers (RX FIFO) (1) If 8 bytes (NUM_RXBYTES = 0x08) are read from the RXFIFO using standard FIFO access (see Section 3.2.4) the following will be read: 3, D...

  • Page 18: Optional Pin Ctrl Radio Control Feature

    CC112X/CC1175 If the radio tries to write to the RX FIFO after it is full or if the RX FIFO is tried read when it is empty, the RXFIFO_OVERFLOW and RXFIFO_UNDERFLOW signals will be asserted and the radio will enter the RX_FIFO_ERR state.
  • Page 19 CC112X/CC1175 The GPIOs can also be used as inputs by setting IOCFGx.GPIOx_CFG = HIGHZ (48). Table 9 CC112X. shows which signals can be input to the GPIO Pin Signal Name Signal Description SERIAL_TX Serial data (TX mode). Used for both synchronous and transparent mode. Synchronous serial mode: Data is captured on the rising edge of the serial clock 1 - 2 Reserved...
  • Page 20 CC112X/CC1175 RSSI_VALID RSSI calculation is valid RSSI Signals RSSI_UPDATE A pulse occurring each time the RSSI value is updated (see Figure 14) RSSI_UPDATE A pulse occurring each time the RSSI value is updated (see Figure 14) AGC_HOLD AGC waits for gain settling see Figure 14) AGC_UPDATE A pulse occurring each time the front end gain has been adjusted...
  • Page 21 CC112X/CC1175 RSSI_STEP_FOUND Collision indication: RSSI step detected after a sync word is found (SYNC_EVENT asserted). The RSSI step is either 3 or 6 dB (configured through AGC_CFG3.RSSI_STEP_THR) RSSI_STEP_EVENT RSSI step detected (single cycle pulse) Reserved (used for test) ANTENNA_SELECT Antenna diversity control. Can be used to control external antenna switch.
  • Page 22 CC112X/CC1175 HIGHZ High impedance (tri-state) EXT_CLOCK External clock (divided crystal clock). The division factor is controlled through the ECG_CFG.EXT_CLOCK_FREQ register field CHIP_RDYn Chip ready (XOSC is stable) HW to 0 (HW to 1 achieved with IOCFGx.GPIOx_INV = 1) 52 - 53 (Reserved (used for test) CLOCK_32K 32 kHz clock output from internal RC oscillator...
  • Page 23 CC112X/CC1175 MARC_STATUS_OUT Description 00000000 No failure 00000001 RX timeout occurred. Only valid in RX mode and when not using eWOR 00000010 RX termination based on CS or PQT. Only valid in RX mode and when not using eWOR 00000011 eWOR sync lost (16 slots with no successful reception). Only valid in Feedback eWOR mode (WOR_CFG1.WOR_MODE = 000b) 00000100 Packet discarded due to maximum length filtering.

  • Page 24: Common Receive And Transmit Configurations

    CC112X/CC1175 Common Receive and Transmit Configurations Modulation Formats CC112X supports amplitude and frequency shift modulation formats. The desired modulation format is set in the MODCFG_DEV_E.MOD_FORMAT register. Optionally, the data stream can be Manchester coded by the modulator and decoded by the demodulator.
  • Page 25 CC112X/CC1175 The symbol encoding can be configured through the SOFT_TX_DATA_CFG.SYMBOL_MAP_CFG (SYMBOL_MAP_CFG = 00b by default). register field as shown in Table 12 Format Symbol Coding SYMBOL_MAP_CFG SYMBOL_MAP_CFG SYMBOL_MAP_CFG SYMBOL_MAP_CFG = = 00b = 01b = 10b „0‟ −Deviation [A 2-(G)FSK +Deviation [A +Deviation[A +Deviation [A...
  • Page 26 CC112X/CC1175 4.1.3 Minimum Shift Keying When using MSK , the complete transmission (preamble, sync word, and payload) will be MSK modulated. MSK modulation is configured by MODCFG_DEV_E.MOD_FORMAT set to 2-(G)FSK modulation and frequency deviation set to ¼ of data rate. Then phase shifts are performed with a constant transition time.
  • Page 27 CC112X/CC1175 ) between −f When using custom frequency modulation there are 129 values (referred to as f OFFSET and +f that can be used (see Equation 1 and Equation 2 in Section 4.1.1 for details on how to program the frequency deviation). f is given by Equation 3.
  • Page 28 CC112X/CC1175 At the receiver, the PN gold sequence is known and is initialized at the beginning of each packet. For every group of 4 incoming symbols, two accumulated distance computation are performed; one assuming that a „0‟ was sent and the other assuming that a „1‟ was sent, and the most likely transmitted bit is chosen.

  • Page 29: Data Rate Programming

    CC112X/CC1175 Data Rate Programming The data rate used in transmit and the data rate expected in receive is programmed by the DATARATE_M and the DATARATE_E configuration settings. The data rate, R , is given by DATA Equation 6 and Equation 7 and is in ksps. Note that DATARATE_M is 20 bits wide and consists of the register fields DATARATE_M_19_16, DATARATE_M_15_8 and DATARATE_M_7_0 found in DRATE2, DRATE1, and DRATE0 respectively.

  • Page 30: Receive Configuration

    CC112X/CC1175 Receive Configuration RX Filter Bandwidth In order to meet different channel width requirements, the RX filter BW is programmable. The CHAN_BW.ADC_CIC_DECFACT and CHAN_BW.BB_CIC_DECFACT register fields control the RX filter BW, together with the CHAN_BW.CHFILT_BYPASS register field and the crystal oscillator frequency. It is recommended to use SmartRF Studio to generate settings for a given RX filter BW.

  • Page 31: Dc Offset Removal

    CC112X/CC1175 DC Offset Removal CC112X supports Low-IF Zero-IF receiver architecture, which FREQ_IF_CFG.FREQ_IF register field. For more information see section 8.11. For Zero-IF the DC offset removal must be enabled by setting DCFILT_CFG.DCFILT_FREEZE_COEFF = 0. The DCFILT_CFG configures the DC filter bandwidth, both during settling period and during tracking. There is a tradeoff between bandwidth and settle time.

  • Page 32: Image Compensation

    CC112X/CC1175 AGC_REF.AGC_REFERENCE Sets the reference value for the AGC. The reference value is a compromise between blocker tolerance/selectivity and sensitivity. The AGC reference level must be higher than the minimum SNR to the demodulator. The AGC reduces the analog front end gain when the magnitude output from the channel filter is greater than the AGC reference level.

  • Page 33: Bit Synchronization

    CC112X/CC1175 Bit Synchronization The bit synchronization algorithm extracts the clock from the incoming symbols. The algorithm requires that the expected data rate is programmed as described in Section 4.2. Re-synchronization is performed continuously to adjust for any offset between the incoming and programmed symbol rate.

  • Page 34: Preamble Detection

    CC112X/CC1175 Preamble Detection CC112X has a high performance preamble detector which can be turned on by setting PREAMBLE_CFG0.PQT_EN = 1. The preamble quality estimator uses an 8 bits wide correlation filter to find a valid preamble. A preamble qualifier value is available through the PQT_SYNC_ERR.PQT_ERROR register field while the threshold is configured with the register field PREAMBLE_CFG0.PQT.
  • Page 35 CC112X/CC1175 be asserted from the first RSSI update. RSSI_VALID is available on a GPIO by setting IOCFGx.GPIOx_CFG = RSSI_VALID (13) or can be read from the RSSI0 register. Carrier Sense (CS) indication will also be affected by the setting of AGC_CFG0.RSSI_VALID_CNT. After the RSSI is valid it will be continuously compared to the CS threshold set in the AGC_CS_THR register, but since the RSSI update rate is given by the RSSI_VALID_CNT register field, this will in practice limit the CS update rate as well.
  • Page 36 CC112X/CC1175 T1: The time the AGC waits after adjusting the front end gain to allow signal transients to decay before the next signal strength measurement can take place. T1 can be calculated using Equation 13. T2: The time the AGC uses to measure the signal strength and potentially adjust the gain. T2 can be calculated using Equation 14.
  • Page 37 CC112X/CC1175 Delay Equation Decimation Factor XOSC DCFILT FREEZE COEFF CARRIER SENSE GATE Decimation Factor XOSC CARRIER SENSE GATE Decimation Factor XOSC DECFACT Decimation Factor XOSC DCFILT FREEZE COEFF Decimation Factor XOSC DECFACT Decimation Factor XOSC DECFACT Decimation Factor XOSC Table 21: D Applicable Delays Current...

  • Page 38: Collision Detector

    CC112X/CC1175 In cases where AGC_CFG1.AGC_SYNC_BEHAVIOR is set to freeze the RSSI value after a sync word is detected, it is important that preamble and sync word is long enough so that the RSSI represent the RSSI of the packet and not of noise received prior to the preamble. Assume a data rate of 1.2 ksps and the following register configurations: CHAN_BW.ADC_CIC_DECFACT = 0 CHAN_BW.BB_CIC_DECFACT = 8...

  • Page 39: Clear Channel Assessment (Cca)

    CC112X/CC1175 RX can be terminated and resumed later. RX can be restarted to receive the new packet. For this to be successful, the new packet must have signal energy that is sufficiently higher than the current packet to allow correct demodulation. This scenario is mainly for high throughput protocols where nodes communicate with several nodes at various distances.

  • Page 40: Listen Before Talk (Lbt)

    CC112X/CC1175 5.11 Listen Before Talk (LBT) CC112X ETSI EN 300 220-1 V2.3.1 [2] has specific requirements for LBT. To simplify compliance built in HW support to automate the LBT algorithm, including random back-offs. The requirements are taken from the ETSI specifications, and a summary is shown below. 5.11.1 LBT Minimum Listening Time “The minimum listening time is defined as the minimum time that the equipment listens for a received signal at or above the LBT threshold level (…..) immediately prior to transmission to determine...

  • Page 41: Transmit Configuration

    CC112X/CC1175 Transmit Configuration PA Output Power Programming PA power ramping is used to improve spectral efficiency of the system by reducing the out of band signal energy created by abrupt changes in the output power. PA output power ramping is used when starting/ending a transmission and this feature is always enabled.

  • Page 42: Packet Handling Hardware Support

    CC112X/CC1175 Packet Handling Hardware Support CC112X has built-in hardware support for packet oriented radio protocols. In transmit mode, the packet handler can be configured to add the following elements to the packet stored in the TX FIFO: A programmable number of preamble bytes An 11, 16, 18, 24 or 32 bit synchronization word A 2 byte CRC checksum computed over the data field.
  • Page 43 CC112X/CC1175 ones zeros (1010∙∙/0101∙∙/ preamble pattern alternating sequence 00110011∙∙/11001100∙∙) programmable through the PREAMBLE_CFG1.PREAMBLE_WORD register field. minimum length preamble programmable through PREAMBLE_CFG1.NUM_PREAMBLE register field. When strobing TX, the modulator will start transmitting a preamble. When the programmed number of preamble bytes has been transmitted, the modulator will send the sync word and then data from the TX FIFO.
  • Page 44 CC112X/CC1175 7.1.4 Arbitrary Length Field Configuration The packet length register, PKT_LEN, can be reprogrammed during receive and transmit (this is also the case for the PKT_BIT_LEN register field in the PKT_CFG0 register). In combination with fixed packet length mode (PKT_CFG0.LENGTH_CONFIG = 00) this opens the possibility to have a different length field configuration than supported for variable length packets (in variable packet length mode the length byte is the first byte after the sync word).
  • Page 45 CC112X/CC1175 7.1.6 Data Whitening From a radio perspective, the ideal over the air data are random and DC free. This results in the smoothest power distribution over the occupied bandwidth. This also gives the regulation loops in the receiver uniform operation conditions (no data dependencies). Real data often contain long sequences of zeros and ones making it difficult to track the data bits.
  • Page 46 CC112X/CC1175 8 (5 ⊕ 0) Table 24: PN9 Whitening Sequence 0x80 ⊕ 0xE1 = 0x61 0xFF ⊕ 0x1D = 0xE2 0x00 ⊕ 0x9A = 0x9A The complete packet will look like this (assume default preamble, sync word, and CRC configuration): 0xAA, 0xAA, 0xAA, 0xAA, 0x93, 0x0B, 0x51, 0xDE, 0x54, 0x61, 0xE2, 0x9A, 0xF9, 0x9D 7.1.7 Data Byte Swap...
  • Page 47 CC112X/CC1175 when PKT_CFG1.BYTE_SWAP_EN = 1, the user should swap the address manually in the DEV_ADDR register in order to match the received address due to the fact that the packet engine compares the address register to the received address before the swapping is done. Figure 19 shows the data sent over the air vs.

  • Page 48: Packet Filtering In Receive Mode

    CC112X/CC1175 Packet Filtering in Receive Mode CC112X supports three different types of packet-filtering; address filtering, maximum length filtering, and CRC filtering. 7.2.1 Address Filtering Setting PKT_CFG1.ADDR_CHECK_CFG to any other value than zero enables the address filtering where the packet handler engine will compare the address field in the packet (see Figure 16) with the programmed node address in the DEV_ADDR register.

  • Page 49: Packet Handling In Transmit Mode

    CC112X/CC1175 7.2.4 Auto Acknowledge By configuring the radio to enter TX after a packet has been received (RFEND_CFG1.RXOFF_MODE = TX) enabling termination on bad packets (RFEND_CFG0.TERM_ON_BAD_PACKET_EN = 1) automatic acknowledgement of packets can be achieved. The Ack. packet should be written to the TX FIFO before RX mode is being entered.

  • Page 50: Tx Fifo And Rx Fifo

    CC112X/CC1175 a) Interrupt Driven Solution The GPIO pins can be used in both RX and TX to give an interrupt when a sync word has been received/transmitted or when a complete packet has been received/transmitted by setting IOCFGx.GPIOx_CFG = PKT_SYNC_RXTX (6). In addition, there are four configurations for the IOCFGx.GPIOx_CFG register that can be used as an interrupt source to provide information on how many bytes are in the RX FIFO and TX FIFO respectively (see 7.6 for more details).

  • Page 51: Transparent And Synchronous Serial Operation

    CC112X/CC1175 Transparent and Synchronous Serial Operation CC112X Several features and modes of operation have been included in the to provide backward compatibility with legacy systems that cannot be supported by the built in packet handling functionality. For new systems, it is recommended to use the built-in packet handling features, as they give more robust communication, significantly offload the microcontroller, and simplify software development.
  • Page 52 CC112X/CC1175 7.7.2 Transparent Serial Mode CC112X does not do any timing recovery and just outputs the hard limited baseband signal. In transparent serial mode the data rate programming does not affect operation. When transparent mode is enabled, the device is set up to resemble a legacy purely analog front end device with baseband output to support legacy pulse position modulation, PWM modulated signals etc.

  • Page 53: Radio Control

    CC112X/CC1175 Radio Control CC112X has a built-in state machine that is used to switch between different operational states (modes). The change of state is done either by using command strobes or by internal events such as TX FIFO underflow. A simplified state diagram is shown in Figure 2. The numbers refer to the state numbers readable from the MARCSTATE.MARC_STATE register field.

  • Page 54: Active Modes

    CC112X/CC1175 Active Modes CC112X has two active modes: receive (RX) and transmit (TX). These modes are activated directly by the MCU by using the SRX and STX command strobes, or automatically by eWOR (RX mode). The MCU can manually change the state from RX to TX and vice versa by using the command strobes.

  • Page 55: Rx Termination

    CC112X/CC1175 RX Termination RX can be terminated by the use of an RX termination timer or based on the assertion of CARRIER_SENSE and/or PQT_REACHED. When RX terminates, the chip will always go back to IDLE if eWOR is disabled and back to SLEEP (via IDLE) if eWOR is enabled. 8.5.1 RX Termination Timer CC112X...
  • Page 56 CC112X/CC1175 Figure 23 shows how the radio behaves when RX_TIME_QUAL (assume that RFEND_CFG0.ANT_DIV_RX_TERM_CFG = 000b). When the RX termination timer expires, the radio will check if a sync word is found or if CARRIER_SENSE or PQT_REACHED has been asserted (to check on PQT_REACHED, PREAMBLE_CFG0.PQT_EN should be set).
  • Page 57 CC112X/CC1175 8.5.2 RX Termination Based on CS If RFEND_CFG0.ANT_DIV_RX_TERM_CFG = 001b the device will use the first RSSI sample to determine if a carrier is present in the channel. If no carrier is present (CARRIER_SENSE not asserted), RX will terminate. The RSSI samples are continually evaluated, and if the RSSI level falls below the threshold (programmed through the AGC_CS_THR register) RX will terminate if not sync is found.

  • Page 58: Enhanced Wake On Radio (Ewor)

    CC112X/CC1175 Enhanced Wake on Radio (eWOR) CC112X The optional enhanced Wake on Radio (eWOR) functionality enables to periodically wake up from SLEEP and listen for incoming packets without MCU interaction. CC112X When the SWOR strobe command is sent on the SPI interface, the will go to the SLEEP state when CSn is released.
  • Page 59 CC112X/CC1175 WOR_CFG1.EVENT1 WOR_EVENT1 [µs] (f = 32 kHz) Event1 RCOSC 187.5 1000 1500 Table 26: Event 1 Equation 21 gives the Event 1 timeout. EVENT Event RCOSC Equation 21: t Event1 An SRX strobe is issued on Event 1 if t is larger than the crystal start-up time.
  • Page 60 CC112X/CC1175 8.6.2 eWOR Modes The different eWOR modes are programmed through the WOR_CFG1.WOR_MODE register field. The three most common eWOR modes are Feedback Mode, Normal Mode, and Legacy Mode. Feedback Mode The radio wakes up on Event 0 and strobes SRX on Event 1. If a good packet is being received the radio enters the state indicated by the RFEND_CFG1.RXOFF_MODE setting.

  • Page 61: Rx Sniff Mode

    CC112X/CC1175 Preamble + sync Payload Time 1.x s 1.x s 1.x s XOSC Start-Up RX Timeout Extra time in RX to receive the packet Time Figure 27: eWOR Mode (RX and TX out of sync.) In this case, the WOR_CAPTURE1 and WOR_CAPTURE0 registers on the receivers would show a higher and higher value for every packet received, indicating that the transmitter is sending at a slower rate than t .
  • Page 62 CC112X/CC1175 8.7.1 RX Sniff Mode Usage RX Sniff Mode is extremely useful in cases where you do not know when the transmitter is going to send a packet. Figure 29 shows ordinary RX mode, where the radio must stay continuously in RX to make sure that it will receive the transmitted packet.

  • Page 63: Rc Oscillator Calibration

    CC112X/CC1175 RC Oscillator Calibration The frequency of the low-power RC oscillator used for the eWOR functionality varies with temperature and supply voltage. In order to keep the frequency as accurate as possible, the RC oscillator should be calibrated whenever possible. Two automatic RC calibration options are available that are controlled by the WOR_CFG0.RC_MODE setting: RC calibration is enabled when the XOSC is running RC calibration is enabled on every 4th time the device is powered up and goes from IDLE to RX...

  • Page 64: Random Number Generator

    CC112X/CC1175 8.9.1 Antenna Diversity Features The device supports antenna diversity by controlling an external RF switch using the ANTENNA_SELECT control signal available on GPIO (IOCFGx.GPIOx_CFG = ANTENNA_SELECT (36)). The device will remember the last antenna used (when not entering SLEEP mode ) and use the last antenna for the next RX or TX transition.

  • Page 65: If Programming

    CC112X/CC1175 The LO divider/band select decoding is shown in Table 29. FS_CFG.FSD_BANDSELECT LO Divider RF Band [MHz] 0000 - 0001 Not in use 0010 820 - 960 0011 Not in use 0100 410 - 480 0101 Not in use 0110 273.3 - 320 0111 Not in use...

  • Page 66: Fs Out Of Lock Detection

    CC112X/CC1175 CC112X has one manual calibration option (using the SCAL strobe), and three automatic calibration options that are controlled by the SETTLING_CFG.FS_AUTOCAL setting: Calibrate when going from IDLE to either RX or TX (or FSTXON) Calibrate when going from either RX or TX to IDLE automatically Calibrate every fourth time when going from either RX or TX to IDLE automatically If the radio goes from TX or RX to IDLE by issuing an SIDLE strobe, calibration will not be performed.

  • Page 67: System Considerations And Guidelines

    CC112X/CC1175 System Considerations and Guidelines Voltage Regulators CC112X contains several on-chip linear voltage regulators that generate the supply voltages needed by the low-voltage modules. These voltage regulators are invisible to the user, and can be viewed as integral parts of the various modules. The user must however make sure that the absolute maximum ratings and required pin voltages are not exceeded.

  • Page 68: Register Description

    CC112X/CC1175 10 Register Description IOCFG3 - GPIO3 Pin Configuration Bit no. Name Reset Description GPIO3_ATRAN 0x00 Analog Transfer Enable 0 Standard digital pad 1 Pad in analog mode (digital GPIO input and output disabled) GPIO3_INV 0x00 Invert Output Enable 0 Invert output disabled 1 Invert output enable GPIO3_CFG 0x06...
  • Page 69 CC112X/CC1175 SYNC_CFG1 - Sync Word Detection Configuration Bit no. Name Reset Description DEM_CFG 0x00 PQT Gating Enable. When PQT gating is enabled the demodulator will not start to look for a sync word before a preamble is detected (i.e. PQT_REACHED is asserted). The preamble detector must be enabled for this feature to work (PREAMBLE_CFG0.PQT_EN = 1) PQT gating disabled...
  • Page 70 CC112X/CC1175 MODCFG_DEV_E - Modulation Format and Frequency Deviation Configuration Bit no. Name Reset Description MODEM_MODE 0x00 Modem Mode Configuration Normal mode DSSS repeat mode. Requires that SYNC_CFG0.SYNC_MODE = 001b or 010b. TX Mode: PKT_CFG2.PKT_FORMAT = 00b RX Mode: PKT_CFG2.PKT_FORMAT = 01b MDMCFG1.FIFO_EN = 0 MDMCFG0.TRANSPARENT_MODE_EN = 0 In RX mode, data is only available on GPIO by configuring...
  • Page 71 CC112X/CC1175 PREAMBLE_CFG1 - Preamble Length Configuration Bit no. Name Reset Description PREAMBLE_CFG1_NOT_USED 0x00 NUM_PREAMBLE 0x05 Sets the minimum number of preamble bits to be transmitted 0000 No preamble 0001 0.5 byte 0010 1 byte 0011 1.5 bytes 0100 2 bytes 0101 3 bytes 0110...
  • Page 72 CC112X/CC1175 IQIC - Digital Image Channel Compensation Configuration Bit no. Name Reset Description IQIC_EN 0x01 IQ Image Compensation Enable. When this bit is set the following must be true: > 2∙RX Filter BW and f + RX Filter BW/2 <= 100 kHz (For CC1125 f + RX Filter BW/2 <= 125 kHz) IQ image compensation disabled...
  • Page 73 CC112X/CC1175 CHAN_BW - Channel Filter Configuration Bit no. Name Reset Description Channel Filter Bypass. Note: CHFILT_BYPASS changes the RX filter bandwidth. CHFILT_BYPASS 0x00 Bypassing the channel filter will reduce the settling time at the expense of selectivity Channel filter enabled XOSC Filter Decimation...
  • Page 74 CC112X/CC1175 MDMCFG1 - General Modem Parameter Configuration Bit no. Name Reset Description When CARRIER_SENSE_GATE is 1, the demodulator will not start to look for a sync word CARRIER_SENSE_GATE 0x00 before CARRIER_SENSE is asserted Search for sync word regardless of CS Do not start sync search before CARRIER_SENSE is asserted FIFO_EN 0x01...
  • Page 75 CC112X/CC1175 MDMCFG0 - General Modem Parameter Configuration Bit no. Name Reset Description MDMCFG0_NOT_USED 0x00 TRANSPARENT_MODE_EN 0x00 Transparent Mode Enable Transparent mode disabled Transparent mode enabled TRANSPARENT_INTFACT 0x00 Transparent Signal Interpolation Factor. The sample rate gives the jitter of the samples and the sample rate is given by Interpolat Factor XOSC...
  • Page 76 CC112X/CC1175 DRATE1 - Data Rate Configuration Mantissa [15:8] Bit no. Name Reset Description Data Rate (mantissa part [15:8]). See DRATE2 DATARATE_M_15_8 0xA9 DRATE0 - Data Rate Configuration Mantissa [7:0] Bit no. Name Reset Description Data Rate (mantissa part [7:0]). See DRATE2 DATARATE_M_7_0 0x2A AGC_REF - AGC Reference Level Configuration...
  • Page 77 CC112X/CC1175 AGC_CFG2 - AGC Configuration Bit no. Name Reset Description START_PREVIOUS_GAIN_EN 0x00 Receiver starts with maximum gain value Receiver starts from previous gain value FE_PERFORMANCE_MODE 0x01 Controls which gain tables to be applied Optimized linearity mode Normal operation mode Low power mode with reduced gain range Reserved AGC_MAX_GAIN 0x00...
  • Page 78 CC112X/CC1175 AGC_CFG0 - AGC Configuration Bit no. Name Reset Description AGC_HYST_LEVEL 0x03 AGC Hysteresis Level. The difference between the desired signal level and the actual signal level must be larger than AGC hysteresis level before the AGC changes the front end gain 2 dB 4 dB...
  • Page 79 CC112X/CC1175 FIFO_CFG - FIFO Configuration Bit no. Name Reset Description CRC_AUTOFLUSH 0x01 Automatically flushes the last packet received in the RX FIFO if a CRC error occurred. If this bit has been turned off and should be turned on again, an SFRX strobe must first be issued FIFO_THR 0x00...
  • Page 80 CC112X/CC1175 FS_CFG - Frequency Synthesizer Configuration Bit no. Name Reset Description FS_CFG_NOT_USED 0x00 FS_LOCK_EN 0x00 Out of Lock Detector Enable Out of lock detector disabled Out of lock detector enabled FSD_BANDSELECT 0x02 Band Select Setting for LO Divider 0000 Not in use 0001 Not in use 0010...
  • Page 81 CC112X/CC1175 WOR_CFG1 - eWOR Configuration, Reg 1 Bit no. Name Reset Description WOR_RES 0x00 eWOR Timer Resolution. Controls the t and RX timeout resolution Event0 EVENT Event RCOSC EVENT 1250 Timeout FLOOR TIME XOSC High resolution Medium high resolution Medium low resolution Low resolution WOR_MODE 0x01...
  • Page 82 CC112X/CC1175 WOR_CFG0 - eWOR Configuration, Reg 0 Bit no. Name Reset Description WOR_CFG_NOT_USED 0x00 DIV_256HZ_EN 0x01 Clock Division Enable. Enables clock division in SLEEP mode Clock division disabled Clock division enabled EVENT2_CFG 0x00 Event 2 Timeout EVENT Event RCOSC EVENT2_CFG WOR_EVENT2 Disabled RC_MODE...
  • Page 83 CC112X/CC1175 PKT_CFG2 - Packet Configuration, Reg 2 Bit no. Name Reset Description PKT_CFG2_NOT_USED 0x00 PKT_CFG2_RESERVED5 0x00 For test purposes only, use values from SmartRF Studio CCA_MODE 0x01 CCA Mode. Selects when to set the CCA signal Always give a clear channel indication Indicates clear channel when RSSI is below threshold Indicates clear channel unless currently receiving a packet Indicates clear channel when RSSI is below threshold and currently not...
  • Page 84 CC112X/CC1175 PKT_CFG0 - Packet Configuration, Reg 0 Bit no. Name Reset Description PKT_CFG0_RESERVED7 0x00 For test purposes only, use values from SmartRF Studio LENGTH_CONFIG 0x00 Packet Length Configuration Fixed packet length mode. Packet Length configured through the PKT_LEN register Variable packet length mode. Packet length configured by the first byte received after sync word Infinite packet length mode Variable packet length mode.
  • Page 85 CC112X/CC1175 RFEND_CFG0 - RFEND Configuration, Reg 0 Bit no. Name Reset Description RFEND_CFG0_NOT_USED 0x00 CAL_END_WAKE_UP_EN 0x00 Enable additional wake-up pulses on the end of calibration. To be used together with the MARC_MCU_WAKEUP signal (MARC_STATUS_OUT will be 0x00) Disable additional wake-up pulse Enable additional wake-up pulse TXOFF_MODE 0x00...
  • Page 86 CC112X/CC1175 PA_CFG1 - Power Amplifier Configuration, Reg 1 Bit no. Name Reset Description FIRST_IPL 0x02 First intermediate power level. The first intermediate power level can be programmed within the power level range 0 - 7/16 in steps of 1/16 SECOND_IPL 0x05 Second intermediate power level.
  • Page 87 CC112X/CC1175 FREQOFF_CFG - Frequency Offset Correction Configuration Bit no. Name Reset Description FREQOFF_CFG_NOT_USED 0x00 FOC_EN 0x01 Frequency Offset Correction Enable Frequency offset correction disabled Frequency offset correction enabled Frequency Offset Correction Configuration. FOC_CFG != 00b enables more narrow FOC_CFG 0x00 RX filter BW than FOC_CFG = 00b but needs longer settle time.
  • Page 88 CC112X/CC1175 TOC_CFG - Timing Offset Correction Configuration Bit no. Name Reset Description Timing Offset Correction Limit. TOC_LIMIT specifies maximum data rate offset TOC_LIMIT 0x00 the receiver are able to handle. TOC_LIMIT != 00b requires 2 - 4 bytes preamble for data rate offset loop to settle <...
  • Page 89 CC112X/CC1175 ECG_CFG - External Clock Frequency Configuration Bit no. Name Reset Description ECG_CFG_NOT_USED 0x00 EXT_CLOCK_FREQ 0x00 External Clock Frequency. Controls division factor 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100...
  • Page 90 CC112X/CC1175 SOFT_TX_DATA_CFG - Soft TX Data Configuration Bit no. Name Reset Description SOFT_TX_DATA_CFG_NOT_USED 0x00 SYMBOL_MAP_CFG 0x00 Symbol Map Configuration. Configures the modulated symbol mapping definition from data bit to modulated symbols. For 2'ary modulation schemes the symbol mapping definition is as follows: SYMBOL_MAP_CFG Data Bit -Dev [A...
  • Page 91 CC112X/CC1175 FREQOFF1 - Frequency Offset (MSB) Bit no. Name Reset Description Frequency Offset [15:8]. Updated by user or SAFC strobe. The value is in two's FREQ_OFF_15_8 0x00 complement format FREQOFF0 - Frequency Offset (LSB) Bit no. Name Reset Description Frequency Offset [7:0]. Updated by user or SAFC strobe. The value is in two's FREQ_OFF_7_0 0x00 complement format...
  • Page 92 CC112X/CC1175 FS_DIG0 Bit no. Name Reset Description FS_DIG0_RESERVED7_4 0x05 For test purposes only, use values from SmartRF Studio RX_LPF_BW 0x02 FS loop bandwidth in RX 101.6 kHz 131.7 kHz 150 kHz 170.8 kHz TX_LPF_BW 0x02 FS loop bandwidth in TX 101.6 kHz 131.7 kHz 150.0 kHz...
  • Page 93 CC112X/CC1175 FS_DSM1 - Digital Synthesizer Module Configuration, Reg 1 Bit no. Name Reset Description FS_DSM1_NOT_USED 0x00 FS_DSM1_RESERVED2_0 0x00 For test purposes only, use values from SmartRF Studio FS_DSM0 - Digital Synthesizer Module Configuration, Reg 0 Bit no. Name Reset Description FS_DSM0_RESERVED7_0 0x03 For test purposes only, use values from SmartRF Studio...
  • Page 94 CC112X/CC1175 FS_VCO1 - VCO Configuration, Reg 1 Bit no. Name Reset Description FSD_VCDAC 0x00 VCO VCDAC Configuration. Used in open-loop CAL mode. Note that avdd is the internal VCO regulated voltage 000000 VCDAC out = min 160 mV 111111 VCDAC out = max avdd - 160 mV FS_VCO1_RESERVED1_0 0x00 For test purposes only, use values from SmartRF Studio...
  • Page 95 CC112X/CC1175 RXMIX - RX Mixer Configuration Bit no. Name Reset Description RXMIX_NOT_USED 0x00 RXMIX_RESERVED1_0 0x01 For test purposes only, use values from SmartRF Studio XOSC5 - Crystal Oscillator Configuration, Reg 5 Bit no. Name Reset Description XOSC5_NOT_USED 0x00 XOSC5_RESERVED3_0 0x0C For test purposes only, use values from SmartRF Studio XOSC4 - Crystal Oscillator Configuration, Reg 4 Bit no.
  • Page 96 CC112X/CC1175 WOR_TIME0 - eWOR Timer Status (LSB) Bit no. Name Reset Description WOR_STATUS_7_0 0x00 eWOR timer counter value [7:0] WOR_CAPTURE1 - eWOR Timer Capture (MSB) Bit no. Name Reset Description WOR_CAPTURE_15_8 0x00 eWOR timer capture value [15:8]. Capture timer value on sync detect to simplify timer re- synchronization WOR_CAPTURE0 - eWOR Timer Capture (LSB) Bit no.
  • Page 97 CC112X/CC1175 RSSI1 - Received Signal Strength Indicator (MSB) Bit no. Name Reset Description RSSI_11_4 0x80 Received Signal Strength Indicator. 8 MSB of RSSI[11:0] RSSI[11:0] is a two's complement number with 0.0625 dB resolution hence ranging from -128 to 127 dBm. A value of -128 dBm indicates that the RSSI is invalid.
  • Page 98 CC112X/CC1175 MARCSTATE - MARC State Bit no. Name Reset Description MARCSTATE_NOT_USED 0x00 MARC_2PIN_STATE 0x02 MARC 2 Pin State Value SETTLING IDLE MARC_STATE 0x01 MARC State 00000 SLEEP 00001 IDLE 00010 XOFF 00011 BIAS_SETTLE_MC 00100 REG_SETTLE_MC 00101 MANCAL 00110 BIAS_SETTLE 00111 REG_SETTLE 01000 STARTCAL...
  • Page 99 CC112X/CC1175 LQI_VAL - Link Quality Indicator Value Bit no. Name Reset Description CRC_OK 0x00 CRC OK CRC check not ok (bit error) CRC check ok (no bit error) 0x00 Link Quality Indicator. 0 when not valid. A low value indicates a better link than what a high value does PQT_SYNC_ERROR - Preamble and Sync Word Error Bit no.
  • Page 100 CC112X/CC1175 AGC_GAIN2 - AGC Gain, Reg 2 Bit no. Name Reset Description AGC_DRIVES_FE_GAIN 0x01 Override AGC gain control AGC controls front end gain Front end gain controlled by registers AGC_GAIN2, AGC_GAIN1, and AGC_GAIN0 AGC_LNA_CURRENT 0x0A Use values from SmartRF Studio AGC_LNA_R_DEGEN 0x01 Use values from SmartRF Studio...
  • Page 101 CC112X/CC1175 MAGN1 - Signal Magnitude after CORDIC [15:8] Bit no. Name Reset Description DEM_MAGN_15_8 0x00 Instantaneous signal magnitude after CORDIC, 17-bit [15:8] MAGN0 - Signal Magnitude after CORDIC [7:0] Bit no. Name Reset Description DEM_MAGN_7_0 0x00 Instantaneous signal magnitude after CORDIC, 17-bit [7:0] ANG1 - Signal Angular after CORDIC [9:8] Bit no.
  • Page 102 CC112X/CC1175 FSCAL_CTRL Bit no. Name Reset Description FSCAL_CTRL_NOT_USED 0x00 FSCAL_CTRL_RESERVED6_1 0x00 For test purposes only, use values from SmartRF Studio LOCK 0x01 Out of Lock Indicator (FS_CFG.FS_LOCK_EN must be 1). The state of this signal is only valid in RX, TX, and FSTXON state 0 FS is out of lock 1 FS out of lock not detected PHASE_ADJUST...
  • Page 103 CC112X/CC1175 TX_STATUS - TX Status Bit no. Name Reset Description TX_STATUS_NOT_USED 0x00 TX_STATUS_RESERVED5 0x00 For test purposes only SYNC_SENT 0x00 Last bit of sync word has been sent TXFIFO_FULL 0x00 Asserted when the TX FIFO is full. De-asserted when the number of bytes is below threshold TXFIFO_OVER_THR 0x00...
  • Page 104 CC112X/CC1175 PRE_TEST Bit no. Name Reset Description PRE_TEST_NOT_USED 0x00 PRE_TEST_RESERVED4_0 0x00 For test purposes only, use values from SmartRF Studio PRE_OVR Bit no. Name Reset Description PRE_OVR_RESERVED7_0 0x00 For test purposes only, use values from SmartRF Studio ADC_TEST - ADC Test Bit no.
  • Page 105 CC112X/CC1175 NUM_TXBYTES - TX FIFO Status (occupied entries) Bit no. Name Reset Description TXBYTES 0x00 Number of bytes in the TX FIFO NUM_RXBYTES - RX FIFO Status (occupied entries) Bit no. Name Reset Description RXBYTES 0x00 Number of bytes in the RX FIFO FIFO_NUM_TXBYTES - TX FIFO Status (free entries) Bit no.

  • Page 106: Soldering Information

    CC112X/CC1175 11 Soldering Information The recommendations for lead-free reflow in IPC/JEDEC J-STD-020 should be followed. 12 Development Kit Ordering Information Orderable Evaluation Module Description CC1120DK Performance Line Development Kit CC1120EMK-169 CC1120 Evaluation Module Kit 169 MHz CC1120EMK-420-470 Evaluation Module Kit 420-470 MHz CC1120EMK-868-915 CC1120 Evaluation Module Kit 868-915 MHz CC1120EMK-955...

  • Page 107: References

    CC112X/CC1175 13 References SmartRF Studio (SWRC176.zip) EN 300 220 V2.3.1: “Electromagnetic compatibility and Radio spectrum Matters (ERM); Short Range Devices (SRD); Radio equipment to be used in the 25 MHz to 1000 MHz frequency range with power levels rang up to 500 mW” (www.etsi.org) SWRU295C Page 107 of 108...

  • Page 108: General Information

    CC112X/CC1175 14 General Information 14.1 Document History Revision Date Description/Changes SWRU295 30.06.2011 Advance Information SWRU295A 24.11.2011 Advance Information. Register description added SWRU295B 06.01.2012 First Release SWRU295C 27.03.2012 Removed the IRQ0M and IRQ0F registers from Section 10. Changed the register description of the IQIC.IQIC_UPDATE_COEFF_EN register field.
  • Page 109 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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