Sharp 1-BIT AMPLIFIER SM-SX1 Service Manual page 43

IC903~IC905 VHiBU2114F+-1: LED Driver (BU2114F)
• Outline
It is the low power consuming CMOS IC which has the latch in the 8-bit shift register and can asynchronously latch the data latched
in the shift register. Since the output (O1 to O8) is the open drain output (Since the protective diode is not provided, the voltage
of VDD or more to max. 7V is applicable, and the drive is possible at 36mA per output up to the total output of 150mA. (Static
operation mode)
Pin No. Port Name Input/Output
1 SIN
2 CK
3 LATCH
4* SOUT
5 EN
6 RST
7 - 9 GND
10 O8
11 O7
12 O6
13 O5
14 O4
15 O3
16 O2
17 O1
18 VDD
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Note) Output of O1 to O8 is an open-drain type, and when the output of the shift register is "H", the output becomes the level "L".
All manuals and user guides at all-guides.com
Input Serial data input terminal
Input Shift clock of shift register
Input When the terminal is turned to "L", the latch output is held.
Moreover, the latch output also varies as the shift register output varies when it is "H".
Output Output of shift register of the final step
Input Enable terminal of O1 to O8
When the terminal is "L", the latch output appears as it is.
However, the output Qn is "L" when the latch output is "H", and Qn is "hi-Z" when the latch
output is "L".
Input Shift register, latch reset
— 0V Power supply
Output Latch output at 8th step of shift register
Output Latch output at 7th step of shift register
Output Latch output at 6th step of shift register
Output Latch output at 5th step of shift register
Output Latch output at 4th step of shift register
Output Latch output at 3rd step of shift register
Output Latch output at 2nd step of shift register
Output Latch output at 1st step of shift register
— +VDD power supply
SIN
CK
LATCH
SOUT
EN
RST
GND
GND
GND
Figure 43 BLOCK DIAGRAM OF IC
Function
V
DD
01
02
03
04
05
06
07
08
– 43 –
SM-SX1/SX1W