Yamaha DVX-S200 Service Manual page 81

A B
DVR-S200 SCHEMATIC DIAGRAM (DIGITAL)
1
Page 82 E8
to MAIN (1) CB106
4M DRAM
5.0
0
1.2 1.6
1.2 1.6
2
1.2 1.6
1.6
1.2
5.0 0
2.7 1.6
2.7 1.5
1.4
2.8
1.3
2.9
2.0
2.0 2.0
2.0
1.8
~
1.1 ~
1.7 ~
1.8
1.7
1.7 1.7
0
5.0
3
X : NOT USED
0
0
EUROPE
0
0
4
5
PLD
6
256K SRAM
7
IC371 : CY62256LL-70SNCT
Static RAM
A5 1 VCC
28
A6 2 WE
27
A7 A4
3 26
A8 A3
4 25
A9 5 24 A2
I/O0
A10 6 23 A1 INPUT BUFFER
I/O1
A10
A11 7 22 OE
A9
I/O2
A12 8 21 A0
A8
A7
A13 9 20 CE I/O3
512 X 512
A6
8
A14 10 19 I/O7 A5
ARRAY
I/O4
A4
I/O0 11 18 I/O6
A3
I/O5
I/O1 12 17 I/O5 A2
I/O2 13 16 I/O4 I/O6
CE POWER
GND 14 15 I/O3 COLUMN
I/O7
DOWN
WE DECODER
OE
C D E
Page 76 B13
to MONO 1500
1.2
1.2
0 1.2
2.5 2.5
0
0
0
0
DSP
4.8
4.8
0
0 3.3
1.3
1.3
Point w (Pin 1 of IC303)
4.8
0
0
3.3
0
3.3
4.7
0
0.3
1.7
4.8
1.7
4.8
1.7
0
0
2
0
3.3
0 4.8
2.5
3.3
0
0
3.3
2.5 3.3
3.3
3.3
ANALOG IN
(DIGITAL)
DECODER
0
IC304 : CS493292-CLR
Audio Decoder
36 8 9 10 11 14 15 16 17 18
A0, SCCLK 7 39 AUDATA2 Parallel or Serial Host Interface
27
DATA7, EMAD7, GPIO7 8 38 DC Compressed
DATA6, EMAD6, GPIO6 9 37 DD 28 Data Input
Frame
DATA5, EMAD5, GPIO5 10 36 RESET Interface
29 Shifter 24-Bit
DATA4, EMAD4, GPIO4 11 35 AGND
DSP Processing
VD2 12 34 VA
Input RAM RAM
DGND2 13 33 FILT1 Buffer
Program Data RAM Output
25
DATA3, EMAD3, GPIO3 14 32 FILT2 Digital Controller
Memory Memory
Audio
DATA2, EMAD2, GPIO2 15 31 CLKSEL
26
Input RAM RAM
DATA1, EMAD1, GPIO1 16 30 CLKIN
Program Data
Interface
DATA0, EMAD0, GPIO0 17 29 CMPREQ, LRCLKN2 22
Memory Memory
RAM Input
Buffer STC
30
PLL
Clock Manager
31
32 33 34 35 24 13 2 23 12 1
F G
Page 86 C3
Page 84 G5
Page 83 H4 or
to SUB (3) CB366
to MAIN (4) CB872
to MAIN (3) CB803
SUB CPU
C424
5.0
4.8
0
0
11.8
2.5
1.7
0
2.5
1.7 0
2.5
1.7
2.5 0
5.0
0
0
2.5
5.0
~ 2.5
0
0
0
0
0
0 0
0
0
0
-11.9
ADC
11.8
ANALOG IN
(DIGITAL) 0
0
1.5
1.5
0
1.5
-11.9
11.8
2.0
0
0
2.0
0
2.0
0
2.5 0.01
-11.9
0 2.5
0 DAC 2.5
2.5
3.3
0
5.0
1.7 11.8
0
2.6 0
1.7
1.3 2.6 0
2.1
1.7 2.6
2.6
1.3 2.6
2.6
0 0
2.0
0
2.1
0
-11.9
11.8
1.8
1.7 1.5
1.7 0
3.3
1.5
1.7
0
1.7
0
3.3
1.7 1.7
5.0
0 0
0
0 3
1.5 0
0
3.2
-11.9
3.2
IC301 : MSM514260E-60JS
4Mbit DRAM
WE
TIMING
VCC 1 40 VSS RAS
GENERATOR
DQ1 2 39 DQ16
DQ2 3 38 DQ15 LCAS
DQ3 4 37 DQ14
UCAS
5 4 19 7 6 20 21
DQ4 5 36 DQ13
VCC 6 35 VSS
37
DQ5 7 34 DQ12 COLUMN
38 9 9
DQ6 DQ11 ADDRESS
8 33
BUFFERS
DQ7 9 32 DQ10
DQ8 10 31 DQ9
44
NC 11 30 NC INTERNAL
REFRESH
43 A0~A8 ADDRESS
CONTROL CLOCK
NC 12 29 LCAS
42 COUNTER
WE UCAS
Output 39 13 28
Buffer
Formatter RAS 14 27 OE
40
41 NC 15 26 A8 ROW
ROW WORD
9 ADDRESS 9
3 A0 16 25 A7 DECODERS DRIVERS
BUFFERS
A1 17 24 A6
A2 A5
18 23 VCC
A3 19 22 A4
ON CHIP
VCC 20 21 VSS
VBB GENERATOR
VSS
H I
Page 87 C1
to FL CB941 to MAIN (1) CB103
C426
560P
C425
REAR_L
FRONT_L
CENTER
0 0
0 2.2
0
0
4.9
0.4
0
0
0
0
4.8
MAIN CPU
0.3
0
4.8
0
1
0
0
VIDEO1_L
0
Point q (Pin 13 of IC308)
(ANALOG IN)
4.8
2.4
0
2.1
4.9
4.9
0
FRONT_L
0
4.6
4.9
0
0
2.4
0
4.8
4.7
4.8
4.9
0.2
CENTER
0.1
0
0
0
0
0
4.9 0
REAR_L
4.9
IC305 : CS4382-KQR
114dB, 192kHz 8ch D/A Converter
48 47 46 45 44 43 42 41 40 39 38 37
DSDA2 1 36 AOUTA2-
DSDB1 2 35 AOUTA2+
DSDA1 3 34 AOUTB2+
VD 4 33 AOUTB2-
GND 5 32 VA
MCLK 6 31 GND
LRCK1 AOUTA3-
7 30
SDIN1 8 29 AOUTA3+
SCLK1 9 28 AOUTB3+
LRCK2 10 27 AOUTB3-
SDIN2 11 26 AOUTA4-
SCLK2 AOUTA4+
12 25
13 14 15 16 17 18 19 20 21 22 23 24
OE
IC306 : CS5351-KSR
108dB, 192kHz, Multi-Bit Audio A/D Converter
I/O
CONTROLLER
OUTPUT
8 8
I/O BUFFERS
CONTROLLER
DQ1~DQ8
COLUMN
INPUT
DECODERS 8 8 1
BUFFERS 17 20 22 23 2 5 10 4 3 12
SENSE I/O FILT+ 24 SERIAL AUDIO
VOLTAGE
16 16
AMPLIFIERS SELECTOR REFERENCE INTERFACE
S/H
+
∆ ∑ DIGITAL HIGH
INPUT AINL 21 LP FILTER
8 8 DECIMATION PASS
BUFFERS –
FILTER FILTER
MEMORY
DQ9~DQ16
CELLS
DAC
OUTPUT S/H
8 8 DIGITAL HIGH
BUFFERS
+ DECIMATION PASS
AINR 16 ∆ ∑
LP FILTER FILTER FILTER
–
DAC
19 7 18 8 6
J K
DVR-S200/NX-P200
IC619 : MM74HCT00SJX
Quad 2 Input NAND
Page 82 B7
A1 1 14 V DD
B1 2 13 B4
Y1 3 12 A4
A2 4 11 Y4
B2 5 B3
10
Y2 6 9 A3
V SS 7 8 Y3
IC618 : MM74HCU04SJX
Hex Inverters
1A 1 14 V DD
1Y 2 13 6A
2A 3 12 6Y
2Y 4 11 5A
3A 5 10 5Y
3Y 6 9 4A
V 7 8 4Y
SS
IC374 : TC74HCT08AF (EL)
Quad 2 Input AND
A1 1 14 V DD
B1 2 13 B4
Y1 3 12 A4
0
0
A2 4
0 11 Y4
4.8
B2 5 10 B3
0
4.6
Y2 6 9 A3
0
4.8 V 7 8 Y3
SS
0
4.8
4.8
0
4.8
IC611, 613–616 :
0
NJM2068MD-TE2
0.1
0.1 Dual OP-Amp
0
0
4.8
OUT 1 8 +V
1 CC
0
5.0
–IN 1 2 7 OUT 2
0 + – + –
0 +IN 1 3 6 –IN 2
4.9
–V 4 5 +IN
0 CC 2
0
0
0
5.1
0
Point e (Pin 8 of IC618)
Page 75 C13
to MONO 1400
DSD_SCLK (M3) SCL/CCLK (M1) SDA/CDIN (M2) AD0/CS (M0) VLC MUTEC1 MUTEC234
RST CONTROL PORT (STAND-ALONE MODE SELECT) EXTERNAL
MUTE CONTROL
AOUTA1+
∆ ∑ DAC
VLS VOLUME CONTROL INTERPOLATION FILTER ANALOG FILTER
AOUTA1-
SCLK1 MIXER
∆ ∑ DAC AOUTB1+
LRCK1 VOLUME CONTROL INTERPOLATION FILTER ANALOG FILTER
AOUTB1-
SCLK2
AOUTA2+
VOLUME CONTROL INTERPOLATION FILTER ∆ ∑ DAC ANALOG FILTER
LRCK2
AOUTA2-
MIXER
SDIN1
VOLUME CONTROL INTERPOLATION FILTER ∆ ∑ DAC ANALOG FILTER AOUTB2+
SDIN2
AOUTB2-
SDIN3
∆ ∑ DAC AOUTA3+
VOLUME CONTROL INTERPOLATION FILTER ANALOG FILTER
SDIN4 AOUTA3-
MIXER
∆ ∑ DAC AOUTB3+
VOLUME CONTROL INTERPOLATION FILTER ANALOG FILTER
AOUTB3-
MCLK
AOUTA4+
VOLUME CONTROL INTERPOLATION FILTER ∆ ∑ DAC ANALOG FILTER
AOUTA4-
÷ 2
MIXER
AOUTB4+
VOLUME CONTROL INTERPOLATION FILTER ∆ ∑ DAC ANALOG FILTER
8
DSDxx AOUTB4-
VQ
FILT+
VD GND GND VA
9 SDATA
* All voltages are measured with a 10M Ω /V DC
electronic volt meter.
15
OVFL * Components having special characteristics are
marked Z and must be replaced with parts
13 M0
having specifications equal to those originally
14 M1
installed.
11
* Schematic diagram is subject to change without
notice.
81