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CN1: Panel Signal from CPU board (reference)
Signal Name
VPCLK
P34
P35
P30
1
□ ○
2
P29
○ ○
○ ○
P25
○ ○
P24
○ ○
P23
○ ○
○ ○
P16
○ ○
P17
○ ○
○ ○
P19
○ ○
P13
○ ○
○ ○
P15
○ ○
P7
○ ○
○ ○
PLCD
○ ○
P9
○ ○
P4
○ ○
○ ○
P3
○ ○
P2
○ ○
○ ○
M
○ ○
SHFCLK
○ ○
50
49
○ ○
FPVDD
FPVEE
GND
+12V
LCD-Kit01A
Pin #
Pin #
Signal Name
1
2
P33
3
4
P31
5
6
P32
7
8
P28
9
10
P27
11
12
P26
13
14
P21
15
16
P22
17
18
P20
19
20
P18
21
22
P14
23
24
P12
25
26
P11
27
28
P10
29
30
PLCD
31
32
P8
33
34
P6
35
36
P5
37
38
P1
39
40
P0
41
42
ENABKL
43
44
FLM
45
46
LP
47
48
GND
49
50
+12V
SHFCLK: Shift Clock. Pixel clock for flat panel data.
FLM:
LP:
M:
ENABKL: power sequencing control for enabling the backlight
FPVEE:
also be configured as ENABKL
CN2 : DF9-31P Panel interface
Pin#
Signalname
Pin#
Signalname
Pin#
Signalname
Pin#
Signalname
Pin#
Signalname
Pin#
Signalname
CN4 :Power Connector for backlight inverter
1
4
9
First Line Marker.Flat Panel equivalent of VSYNC.
Latch Pulse(may also be called CL1).
M signal for panel AC drive control (may also be called
ACDCLK).
Power sequencing control for panel bias voltage VEE. May
1
2
3
GND
SHFCLK
LP
7
8
9
P19
P20
P21
13
14
15
P10
P11
P12
19
20
21
GND
P2
P3
25
26
27
P7
GND
M
31
N.C.
1
+12V
□
2
FPBACK
○
○
3
GND
○
4
VR
LCD-Kit01A
4
5
6
FLM
GND
P18
10
11
12
P22
P23
GND
16
17
18
P13
P14
P15
22
23
24
P4
P5
P6
28
29
30
PLCD
PLCD
N.C
10
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