Philips 43PFL4902/F7 Service Manual page 50

Digital Main 3 Schematic Diagram
1 NOTE:
The order of pins shown in this diagram is different from that of actual IC3001.
IC3001 is divided into nine and shown as IC3001 (1/9) ~ IC3001 (9/9) in this Digital Main Schematic Diagram Section.
DIGITAL MAIN CBA UNIT
4
C9006
1000P
JK9301
ANT-IN
C9001 C9002 C9018
L9007
330P 120P 82P
5.6nH
L9001 C9014 C9003 C9015
270nH VARISTOR 180P 2P
3
L9002
220nH
2
1
M
C9011 C9012
X9001
1000P 1000P
24MHz
1 4
2 3
18 17 16 15 14 13
L9003
270nH
19 RF-REF NU 12
C9022 C9021
C9004 L9004
1P 1P
150P 270nH
20 RF-IP OUTPUT 11
I/F
C9017
1P
21 GND 10
C9005
150P
DSP
22 PGA ADC VCC 9
/FILTER
L9005 C9010 C9023
270nH 1000P 1P
23 GND GND 8
RF
L9006
AGC
270nH 24 NU VDDL 7
C9008 C9009
1000P 1
IC9001
SI2151 1 2 3 4 5 6
DIGITAL/ANALOG
TV TUNER
C9019 C9007
OPEN R9001 R9003 0.1
100 1K
R9002
C9020
100
OPEN
C3009
OPEN
N O
C9013 C9016 C9024 C9025
0.1 1 OPEN OPEN
R9005
100
R9004
100
C3014 C3013
33P 33P
C3006
OPEN
C3003 L3001
OPEN OPEN
C3005
OPEN
R3005
47
D3001 D3002 D3003
C3008 C3010 C3011
MM5Z5V6B MM5Z5V6B MM5Z5V6B
10 33P 33P
R3006
C3012 D3004 C3001
100
0.1 MM5Z5V6B 0.022
P
10-7
CN3002 (NO CONNECTION)
1 IF-AGC
2 SCL
3 SDA
4 GND
*1
IC3001(3/9)
MSD95M0D-3-005D
DIGITAL SIGNAL PROCESS
/MAIN MICRO CONTROLLER
C3004
R3001
0.1
0
AM2
DEMODULATOR
/MPEG
C3002
R3003
0.1 DECODER
0
AL2
AK1 NU TO DIGITAL TO DIGITAL
MAIN 6 MAIN 6
AK2 NU
IC3001(6/9) IC3001(6/9)
R3004
47 AL7 NU
AM7 NU
R3007
AM8 NU
4.7K
AK7 NU
R3008
AL5 NU
4.7K
AM5 NU
R4 TU-SCL
R5 TU-SDA
AK3 IF-AGC
R3002
L3003 10K
2.2uH
L3002
0
C3007
0.1
CONTINUE
DIGITAL 9
P-ON+3.3V
Q R
PL17.06SCD3