Sanyo DC-MCR60 Service Manual page 10

IC BLOCK DIAGRAM & DESCRIPTION
IC102 LC78629E (DSP for CD Player)
No. Symbol I/O Function description
Defect detection signal(DEF) input pin.
1 DEFI I
(Must be connected to 0V when unused.)
Test input pin. A pull-down resistor is built-in.
2 TAI I
Must be connected to 0V.
3 PDO O External VCO control phase comparator output pin.
4 VVSS - Internal VCO ground pin.Must be connected to 0V.
PLL
PDO output current adjustment resistor
5 ISET AI
connection pin.
6 VVDD - Internal VCO power supply pin.
7 FR AI
VCO frequency range adjustment.
8 VSS - Digital system ground pin. Must be connected to 0V.
9 EFMO O EFM signal output pin.
Slice level
control
10 EFMIN I EFM signal input pin.
Test input pin. A pull down resistor is built in.
11 TEST2 I
Must be connected to 0V.
12 CLV+ O
Disk motor control output.
Can be set to three-value output by microprpcessor command.
13 CLV- O
Rough servo/phase control automatic switching monitor
output pin.
14 V/*P O
Outputs a high level during rough servo and a low level.
Track detection signal input pin. This is a Schmidt input.
15 HFL I
Tracking error signal input pin. This is a Schmidt input.
16 TES I
Tracking off output pin.
17 TOFF O
Tracking gain switching output pin.
18 TGL O
Increase the gain when low.
Track jump output.
19 JP+ O
Three-value output is also possible when specified by
microprocessor command.
20 JP- O
EMF data playback clock monitor pin.
21 PCK O
Output 4.3218MHz when the normal-speed playback phase
command.
Synchhronization signal detection output pin. Output a high
level when the synchronization signal detected from the EFM
22 FSEQ O
signal and the internaly generated synchronization signal range.
Peripheral circuitry 5V system power suply pin.
23 VDD -
General-purpose 1
24 CONT1 I/O
input/output pin.
General-purpose 2
25 CONT2 I/O
input/output pin. Controlled by serial data commands.
From the microprocessor.
General-purpose 3 Any of these that are unused must
26 CONT3 I/O
input/output pin. be either set up as input pin and
connected to 0V, or set up as output
General-purpose 4 pin and left open.
27 CONT4 I/O
input/output pin.
General-purpose 5
CONT5 I/O
28
input/output pin.
De-emphasis monitor pin.
A high level indicates playback of a de-emphasis disk,
EMPH/
29 O
General-purpose 6 output pin.
CONT6
Rest to EMPH function.
C2 flag output pin.
30 C2F O
Digital output pin. (EIJA format)
DOUT O
31
Test input pin.
32 TEST3 I
A pull-down resistor is built in. Must be connected to 0V.
All manuals and user guides at all-guides.com
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DEFI 1
_
TAI 2
_
PDO 3
_
VVSS 4
_
ISET 5
_
VVDD 6
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FR 7
_
VSS 8
_
EFMO 9
_
EFMIN 10
_
TEST2 11
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CLV+ 12
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CLV- 13
_
V *P 14
_
HFL 15
_
TES 16
Output pin
No. Symbol I/O
to rest
-
33
34
-
35
36
37
38
-
39
Incertitude
40
-
41
-
42
L output
43
L output
44
45
-
46
-
47
H output
48
Incertitude
49
50
L output
51
L output
52
53
Incertitude
54
-
55
56
57
Input
58
59
60
61
62
L output
63
Incertitude
64
Incertitude
Note) The same potential must be suplied to all power supply pins, i.e., VDD,VVDD,LVDD,RVDD
-
- 9 -
_
48 EFLG
_
47 SBSY
_
46 XVSS
_
45 XIN
_
44 XOUT
_
43 XVDD
_
42 MUTER CONT8
_
41 RVDD
_
40 RCHO
_
39 RVSS
_
38 LVSS
_
37 LCHO
_
36 LVDD
_
35 MUTEL CONT7
_
34 PCCL
_
33 TEST4
Function description
Test input pin.
TEST4 I
A pull-down resistor is built in. Must be connected to 0V.
General-purpose I/O command identification pin.
A pull-down resistor is built in.
Used operate similarly to LC78622E connected to open or 0V.
PCCL I
H ; Must be connected to general-purpose port command.
L ; Be able to all command control.
Left channel mute output pin, General-purpose 7
MUTEL/
O output pin.
CONT7
Rest to MUTEL function.
Lch
LVDD - one-bit Left channel power supply pin.
DAC
LCHO O Left channel output pin.
LVSS - Left channel ground pin. Must be connected to 0V.
RVSS - Right channel ground pin. Must be connected to 0V.
RCHO O Right channel output pin.
Rch
RVDD - one-bit Right channel power supply pin.
DAC
Right channel mute output pin, General-purpose 8
MUTER/
O output pin.
CONT8
Rest to MUTER function.
XVDD - Crystal oscillator power supply pin.
O
XOUT
Connections for a 16.934MHz crystal oscillating circuit
ground pin.
XIN I
XVSS - Crystal oscillator ground pin. Must be connected to 0V.
SBSY O Subcode block synchronization signal pin.
O C1,C2,signal and double error correction monitor pin.
EFLG
Subcode P,Q,R,S,T,U,V and W output pin.
PW O
Subcode frame synchronization signal output pin.
SFSY O
This signal falls when the subcode are in the standby stase.
Subcode readout clock input pin. This is a Schmitt input.
SBCK I
(Must be connected to 0V when unused.)
Output for the 7.35kHz synchronization signal divided from
FSX O
the crystal oscillator pin.
Subcode Q output standby output pin.
WRQ O
Read/ write control input pin. This is a Schmidt input.
RWC I
SQOUT O Subcode Q output pin.
COIN I Command, data input pin from control microprocessor.
Input for both the command input acquisition clock and the
*CQCK I SQOUT subcode readout clock input pin.
This is Schmidt input.
Reset input pin.
*RES I
This pin must be set low briefly after power is first applied.
O Test output pin. Leave open. (Notmally output a low level.)
TST11
16.9344MHz clock output pin.
16M O
4.2M O 4.2336MHz clock output pin.
Test input pin. A pull-down resistor is built in.
I
TEST5
Must be connected to 0V.
VDD3V - Internal circuit 3.3V system power supply pin.
Test input pin.
TEST1 I
A pull-down resistor is built in. Must be connected to 0V.
and XVDD.
Output pin
to rest
-
-
H output
-
-
-
-
-
-
H output
-
-
-
Incertitude
Incertitude
Incertitude
Incertitude
-
Incertitude
Incertitude
-
Incertitude
-
-
-
L output
Clock output
Clock output
-
-
-