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Goodix GR551 Series Hardware Design Manuallines

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GR551x Hardware Design Guidelines
Version: 2.1
Release Date: 2021-06-15
Shenzhen Goodix Technology Co., Ltd.

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Summary of Contents for Goodix GR551 Series

  • Page 1 GR551x Hardware Design Guidelines Version: 2.1 Release Date: 2021-06-15 Shenzhen Goodix Technology Co., Ltd.
  • Page 2 Copyright © 2021 Shenzhen Goodix Technology Co., Ltd. All rights reserved. Any excerption, backup, modification, translation, transmission or commercial use of this document or any portion of this document, in any form or by any means, without the prior written consent of Shenzhen Goodix Technology Co., Ltd is prohibited.

  • Page 3: Preface

    Introduced the GR5515I0ND SoC: • Added “GR5515I0ND” for pinout details; 2020-08-30 • Added “External Flash” to describe recommended external Flash for GR5515I0ND; • Added the reference schematic for GR5515I0ND in “Reference Design”; Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 4 • Updated descriptions in “Power Supply Scheme”, “Power Supply”, “Clock”, “ESD Schematic Design”, “PCB Layout Design” and “Two-layer PCBs in QFN Packages”. Add a note of not recommended for new designs for GR5515RGBD. 2021-06-15 Updated the recommended external flash models for GR5515I0ND. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 5: Table Of Contents

    3.2.3.2 RF Input Power Supply........................34 3.2.4 Clock................................35 3.2.5 RFIO Port..............................36 3.2.6 Grounding..............................37 3.2.7 ESD Protection Design..........................37 3.2.7.1 System-level ESD Design........................38 3.2.7.2 ESD Considerations in Production, Transport, and Debugging............43 Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 6 7.4 Rework Guideline.............................. 72 7.4.1 Component Removal..........................73 7.4.2 Site Redress...............................73 7.4.3 Solder Paste Printing..........................73 7.4.4 Component Placement..........................74 7.4.5 Component Attachment........................... 74 7.5 RoHS Compliant..............................74 7.6 SVHC Materials (REACH)............................74 7.7 Halogen Free..............................74 Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 7: Gr551X Overview

    1 GR551x Overview The Goodix GR551x family is a single-mode, low-power Bluetooth 5.1 System-on-Chip (SoC). It can be configured as a Broadcaster, an Observer, a Central, or a Peripheral and supports the combination of all the above roles, making it an ideal choice for Internet of Things (IoT) and smart wearable devices.
  • Page 8 Built-in temperature and voltage sensors ◦ 4 x Hardware timers ◦ 1 x AON hardware timer ◦ 2 x Watchdog timers(1 System Watchdog Timer and 1 Always-on watchdog timer) ◦ Calendar timer ◦ Wake-up comparator Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 9: Block Diagram

    BGA55: 3.5 mm x 3.5 mm ◦ QFN40: 5 mm x 5 mm • Operating temperature range: -40°C to +85°C 1.2 Block Diagram The block diagram of GR551x is shown in the figure below. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 10 Cache Ctrl. WDT . LP Comp. Ctrl . Cores PMU Subsystem MCU Subsystem Figure 1-1 GR551x block diagram Note: For more details of each module in this block diagram, see GR551x Datasheet. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 11: Pinout

    MSIO1 GPIO_7 MSIO2 GPIO_8 MSIO3 GPIO_9 MSIO4 GPIO_10 RTC_P DigitalI/O & supplies pin Analog pin RF pin Figure 2-1 GR5515IGND QFN56 package pinout Table 2-1 shows pin descriptions of GR5515IGND QFN56 package. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 12 1 µF capacitor. VREG Feedback pin from switching regulator DC-DC Converter switching node DC-DC converter supply and general battery VSS_BUCK VBATL Power supply input RTC_N RTC terminal -, 32.768 kHz crystal - Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 13 General purpose I/O VDDIO0 GPIO_31 Digital I/O General purpose I/O VDDIO0 GPIO_30 Digital I/O General purpose I/O VDDIO0 GPIO_26 Digital I/O General purpose I/O VDDIO0 GPIO_27 Digital I/O General purpose I/O VDDIO0 Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 14: Gr5515I0Nd Qfn56

    2.2 GR5515I0ND QFN56 Figure 2-2 shows the pin assignments of GR5515I0ND QFN56 package (top view). The pins (Pin 43 to Pin 53) of GR5515I0ND QFN56 package are different from those of GR5515IGND QFN56 package. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 15 Pin # Pin Name Pin Type Description/Default Function Voltage Domain Synthesizer VCO supply. RF supply. VDD_VCO/VDD_RF Analog/RF supply Connect to VREG. Analog/RF RX input and TX output VBATT_RF Analog/RF Supply Connect to VBATL. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 16 RTC terminal +, 32.768 kHz crystal + Configurable to be a GPIO mixed signal (ADC MSIO4 Mixed Signal I/O VBATL interface) Configurable to be a GPIO mixed signal (ADC MSIO3 Mixed Signal I/O VBATL interface) Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 17 General purpose I/O VDDIO0 GPIO_30 Digital I/O General purpose I/O VDDIO0 GPIO_26 Digital I/O General purpose I/O VDDIO0 VDD_AMS Analog/RF Supply AMS supply. Connect to VREG. Analog/RF XO Crystal - Analog/RF XO Crystal + Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 18: Gr5515Rgbd Bga68 (Nrnd)

    VREG VBATH VBATL MSIO1 RTC_N RTC_P AON_GPIO2 CORE_1V RF pin Digital I/O & supplies pin Analog pin Figure 2-3 GR5515RGBD BGA68 package pinout Table 2-3 shows pin descriptions of GR5515RGBD BGA68 package. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 19 General purpose I/O, default SWDIO VDDIO1 DGND Digital GND Digital Ground DGND Digital GND Digital Ground AON_GPIO1 Digital I/O Always-on general purpose I/O VDDIO0 AON_GPIO7 Digital I/O Always-on general purpose I/O VDDIO0 Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 20 Digital I/O Always-on general purpose I/O VDDIO0 GPIO7 Digital I/O General purpose I/O VDDIO1 GPIO10 Digital I/O General purpose I/O VDDIO1 Connected internally VIO_LDO_OUT Analog/PMU Output of On-Chip I/O supply regulator. to VDDIO0 Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 21: Gr5515Ggbd Bga55

    RTC_P Analog/PMU RTC terminal +, 32.768 kHz crystal + AON_GPIO2 Digital I/O Always-on general purpose I/O VDDIO0 2.4 GR5515GGBD BGA55 Figure 2-4 shows the pin assignments of GR5515GGBD BGA55 package (top view). Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 22 Voltage Domain VDD_RF Analog/RF supply RF supply: 1.1 V VDD_VCO Analog/RF supply Synthesizer VCO supply: 1.1 V Analog/RF XO crystal + Analog/RF XO crystal - VDD_AMS Analog/RF supply AMS supply 1.1 V Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 23 Configurable to be a GPIO mixed signal (ADC MSIO0 Mixed Signal I/O VBATL interface) GPIO5 Digital I/O General purpose I/O VDDIO1 GPIO6 Digital I/O General purpose I/O VDDIO1 DGND2 Digital GND Digital ground Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 24: Gr5513Bend Qfn40

    Analog /PMU Input from battery VREG Analog /PMU Feedback pin of switch regulator Analog /PMU DC-DC converter switching node PMUGND Analog /PMU DC-DC converter & general battery GND pin 2.5 GR5513BEND QFN40 Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 25 RX input and TX output VBATT_RF Analog/RF Connect to VBATL. GPIO_0 Digital I/O General purpose I/O, default SWDCLK VDDIO1 GPIO_1 Digital I/O General purpose I/O, default SWDIO VDDIO1 GPIO_2 Digital I/O General purpose I/O VDDIO1 Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 26 If TEST_MODE = 0, the chip is in normal operation mode. AON_GPIO_0 Digital I/O Always-on general purpose I/O VDDIO0 AON_GPIO_1 Digital I/O Always-on general purpose I/O VDDIO0 AON_GPIO_2 Digital I/O Always-on general purpose I/O VDDIO0 Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 27 Digital I/O General purpose I/O VDDIO0 GPIO_26 Digital I/O General purpose I/O VDDIO0 VDD_AMS Analog/RF AMS supply. Connect to VREG. Analog/RF XO Crystal - Analog/RF XO Crystal + Analog/RF Test Mux + output Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 28: Minimal Design For Gr551X Soc

    Low Power DC-DC Digital LDO Control Switch Stacked Flash Always ON Power Power Power Power Island VDDIO Island #n Island #1 Power Island #1 Island #1 Figure 3-1 Power management block diagram Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 29: Power Supply Scheme

    The detailed pin descriptions and connection guidance are as follows: • VDD_VCO/RF: internal RF block supply, connected to V1P0 (output power net of DC-DC switching regulator) and a 0.1 µF filter capacitor Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 30 CAP CER X5R 10% 6.3 V 2.2 μF 0603 GRM188R61C225KE15D C4, C7, C8, C14 CAP CER X7R 10% 10 V 0.1 µF 0402 Murata GRM155R71A104KA01D CAP CER X5R 10% 6.3 V 1 µF 0402 Samsung Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 31: I/O Ldo

    I/O domain MSIO, corresponding to reference voltage levels at VDDIO0, VDDIO1, and VBATL respectively. Note that VDDIO0 is connected to VIO_LDO_OUT internally, and is not bonded to any package pins. Figure 3-3 is a circuit diagram showing the connection between VIO_LDO_OUT and the I/O domains. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 32 I/O LDO is set to off mode automatically based on eFuse configurations after system startup. • Use VIO_LDO_OUT as input for the VDDIO0 domain, and connect VIO_LDO_OUT to the external power supply of 3.3 V or VBATL. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 33: Clock

    -40°C to +85°C -40°C to +85°C Size (L x W x H, mm) 2.5 x 2.0 x 0.60 2.5 x 2.0 x 0.60 2.0 x 1.6 x 0.60 2.5 x 2.0 x 0.60 Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 34: Khz Clock

    1.6 x 1.0 x 0.50 Note: To ensure system stability and low power consumption, load capacitance of the 32.768 kHz crystal oscillator shall be within the range from 6 pF to 9 pF. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 35: Introduction

    The modulated carrier is transmitted to the antenna through a low-power or high-power PA path. The antenna radiates the amplified carrier wave through electromagnetic waves. Note: RF and digital clocks are generated from the XO. 3.1.3.2 RF Scheme Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 36: I/O Pins

    Phase and duty cycle of each channel can be configured via registers. 3.1.5 SWD Interfaces GR551x connects to J-Link for modulation by using Serial Wire Debug (SWD) interfaces. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 37: External Flash

    Therefore, it is recommended that you choose a proper Flash memory that meets the electrical characteristics and functional requirements based on actual project demands. 3.2 PCB Design and Layout Guideline Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 38: Pcb Layer Stackup

    All components operating at high frequency should have their layout made as compact as possible. This will prevent the cross-coupling between lines and also minimize the parasitic effects which will have a negative impact on the operating parameters. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 39: Power Supply

    GND pin as possible. It is recommended to connect the C15 GND pin to VSS_BUCK by using GND Polygon Plane, so that the return path of the power can be kept minimal. Figure 3-7 Reference layout and routing for DC-DC switching regulator Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 40: Rf Input Power Supply

    VDD_VCO, VDDIO1, and VIO_LDO_OUT respectively, and C2, C3, and C6 (15 pF capacitors) close to VDD_AMS, VBATT_RF, and VDD_RF respectively. C5 (1 μF capacitor) is placed close to pin VDD_DIGCORE_1V, as shown in Figure below. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 41: Clock

    It is recommended to shield the routes of the 32 MHz crystal. If the ground below the crystal is clean and no crosstalk or interference is involved, provide openings on the pad underneath the crystal (as shown in Figure 3-11), which helps to reduce parasitic capacitance. Figure 3-10 Clock PCB Ref of GR5515RGBD (reference) Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 42: Rfio Port

    Components in this network must be placed as close as possible to the RFIO pin. Try to place the first component no further than 1 mm from the RFIO pin. Figure 3-12 shows the PCB layout of the RF port. Figure 3-12 GR551x routing on a PCB Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 43: Grounding

    Make sure a ground via is placed right next to the TRX pin. • For the BGA packages, place ground vias as close as possible to the ground balls. 3.2.7 ESD Protection Design Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 44: System-Level Esd Design

    Table 3-12 Model selection for ferrite beads Parameters Description Min. Typ. Max. Impedance@100 MHz (Ω) Impedance @ 100 MHz 600 Ω (mA) Rated operating current 900 mA Max. (mΩ) Maximum DC resistance 230 mΩ Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 45 5 µA is recommended. To reset the system by using SGM820 as the external WDT, the WDT timeout period can be set with an external capacitor. Set WDT countdown value with SGM820A-X (standard): Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 46 It is recommended not to place pads of charging ports (CHAR+ and CHAR-) and GR551x SoC on the same layer. However, if the pads and GR551x SoC are on the same layer, a minimum distance between the two at 5 mm shall be guaranteed. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 47 It is recommended to shield the I/O pins and ESD susceptible signals with GND traces. Figure 3-16 Improper I/O routing at board edge (not shielded by GND traces) Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 48 Connecng to filter capacitor with long wires Figure 3-19 Improper routing for a capacitor (as an example) 3.2.7.1.3 Product Structural Design • Shell gaps shall be sealed to prevent static electricity from setting in. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 49: Esd Considerations In Production, Transport, And Debugging

    Use an antistatic bag/tray to hold the SoC. • Countermeasures against ESD are essential for soldering irons, welding tables, and test instruments. • Strictly comply with ESD preventive requirements for the production line during production and transport. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 50: Reference Design

    Reference Design 4 Reference Design 4.1 Reference Schematic Diagram Figure 4-1 is the reference schematic for GR5515IGND QFN56 package. Figure 4-1 Reference schematic for GR5515IGND QFN56 package Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 51 Reference Design Figure 4-2 is the reference schematic for GR5515I0ND QFN56 package. Figure 4-2 Reference schematic for GR5515I0ND QFN56 package Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 52 Reference Design Figure 4-3 is the reference schematic for GR5515RGBD BGA68 package. Figure 4-3 Reference schematic for GR5515RGBD BGA68 package Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 53 Reference Design Figure 4-4 is the reference schematic for GR5515GGBD BGA55 package. Figure 4-4 Reference schematic for GR5515GGBD BGA55 package Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 54: Pcb Layout Reference Design

    RF route is not higher than 50 Ω, provide openings on the second layer, and use the third layer (PCB layer stackup: 0.6 mm, impedance: up to 50 Ω, as shown in Figure 4-6) as the reference plane. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 55 Details for the PCB layout reference design are provided below. Top layer This layer is used for component layout and routing of key signals such as RF. Figure 4-7 Top layer design for 4-layer PCB (QFN56) Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 56 Figure 4-9 L3 design for 4-layer PCB (QFN56) Bottom layer This layer is used for filter components layout and signal routing. Filter components should be as close to the corresponding IC pins as possible. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 57: Two-Layer Pcbs In Qfn Packages

    4-11, the top layer is used for component layout and routing of key signals such as RF), so that the bottom layer can be as complete as possible. Figure 4-11 Top layer design for 2-layer PCB Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 58: External Flash Connection For Gr5515I0Nd

    Flash shall be as close to the IC as possible to minimize the QSPI route. QSPI route lengths should be matched, with the tolerance within 50 mil. Figure 4-13 is a reference design for the PCB layout of GR5515I0ND. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 59: Four-Layer Pcbs In Bga68 Package(Nrnd)

    This is the reference ground plane for the ground return path of the 50 Ω RF transmission line. Two openings are provided underneath the signal output pads of the 32 MHz crystal on L2, to reduce the parasitic load capacitance of the crystal. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 60 Figure 4-16 L3 design for 4-layer PCB (BGA68) Bottom layer This layer is used for filter components layout and signal routes. Filter components should be as close to the corresponding IC pins as possible. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 61 Reference Design Figure 4-17 Bottom layer design for 4-layer PCB (BGA68) Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 62: Faq

    I/O pin configurations. How to properly configure I/O pins before GR551x goes to sleep? • Issue Analysis The power consumption of GR551x in sleep mode is high, and it may be because I/O pins are not properly configured. ◦ I/O pins are at floating state. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 63: Can The Rf Pi Circuits Be Simplified Or Removed

    Smith chart from the vector network analyzer. However, for matching of other indicators (such as antenna gain and directionality), you are recommended to seek help from professional antenna factories. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 64: Glossary And Abbreviations

    Queued Serial Peripheral Interface RoHS Restriction of Hazardous Substances Directive Software Development Kit System-on-Chip Serial Peripheral Interface SVHC Substance of Very High Concern Serial Wire Debug Universal Serial Bus UART Universal Asynchronous Receiver Crystal Oscillator Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 65: Appendix: Qfn And Bga Assembly Guideline

    GR551x, certain constraints are added to IPC’s methodology. The pad pattern developed here includes considerations for lead and package tolerances. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 66: Package Information

    QFN40 packages to support different environmental requirements. 7.1.1 GR5515IGND/GR5515I0ND QFN56 GR551x QFN56, including GR5515IGND and GR5515I0ND, is 56-pin and 7 x 7 x 0.75 mm QFN package. It is qualified for MSL3. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 67 Figure 7-3 GR5515IGND/GR5515I0ND QFN56 package outlines Note: Drawing is not to scale. Table 7-2 GR5515IGND/GR5515I0ND QFN56 package dimensions Dimensions in mm Dimensions in inch Symbol 0.700 0.750 0.800 0.028 0.030 0.032 0.000 0.020 0.050 0.000 0.001 0.002 Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 68: Gr5515Rgbd Bga68 (Nrnd)

    5.3 x 5.3 +0.1/–0.1 mm BGA Ball Count Total Thickness 0.88 +0.1/–0.1 mm BGA Ball Pitch 0.50 Ball Diameter 0.25 Ball Height 0.18 Figure 7-4 below shows the GR5515RGBD BGA68 package outlines. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 69 Dimension in inch Symbol 0.780 0.880 0.980 0.031 0.035 0.039 0.130 0.180 0.230 0.005 0.007 0.009 0.650 0.700 0.750 0.026 0.028 0.030 0.140 0.170 0.200 0.006 0.007 0.008 5.200 5.300 5.400 0.205 0.209 0.213 Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 70: Gr5515Ggbd Bga55

    +0.1/–0.1 mm BGA Ball Count Total Thickness 0.60 +0.05/–0.05 mm mm BGA Ball Pitch 0.40 Ball Diameter 0.20 Ball Height 0.12 +0.03/–0.03 mm mm The figure below shows the GR5515GGBD BGA55 package outlines. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 71 Dimension in mm Dimension in inch Symbol 0.550 0.600 0.650 0.022 0.024 0.026 0.090 0.120 0.150 0.004 0.005 0.006 0.435 0.475 0.505 0.017 0.019 0.020 0.350 REF. 0.014 REF. 0.125 REF. 0.005 REF. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 72: Gr5513Bend Qfn40

    QFN Pad Count Total Thickness 0.75 ±0.05 mm QFN Pad Pitch 0.40 Pad Width 0.20 ±0.05 mm Exposed Pad Size 3.7 x 3.7 ±0.1 mm The figure below shows the GR5513BEND QFN40 package outlines. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 73 0.008 0.010 5.000 BSC. 0.197 BSC. 5.000 BSC. 0.197 BSC. 0.400 BSC. 0.016 BSC. 3.600 3.700 3.800 0.142 0.146 0.150 3.600 3.700 3.800 0.142 0.146 0.150 0.300 0.400 0.500 0.012 0.016 0.020 Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 74: Board Mounting Guideline

    Aspect ratio = W/T L and W are the aperture length and width, and T is stencil thickness. For optimum paste release, the area and aspect ratios should be greater than 0.66 and 1.5 respectively. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 75: Via Types And Solder Voiding

    Electroless nickel/Immersion gold (ENIG) • Immersion silver • Immersion gold Selection of a suitable finish will depend on end users’ requirements for board design, assembly process, handling/ storage, and cost. 7.2.2.2 PCB Materials Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 76: Smt Printing Process

    An optimized reflow process is the key to ensure successful lead-free assembly, high yield and long-term solder joint reliability. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.
  • Page 77 150°C – 200°C Preheat time (ts) 60 seconds – 180 seconds Time above TBL, 217°C (TL) 60 seconds – 150 seconds Time within 5°C of peak temperature (tp) 20 seconds – 40 seconds Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 78: Rework Guideline

    Because reflow of adjacent parts is not desirable during rework, the proximity of other components may further complicate this process. Because of the product dependent Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 79: Component Removal

    The solvent is usually specific to the type of paste used in the original assembly and paste manufacturer’s recommendations should be followed. 7.4.3 Solder Paste Printing Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

  • Page 80: Component Placement

    Agency (ECHA) on October 28, 2008 Regulation (EC) No 1907/2006 concerning Registration, Evaluation, Authorisation and Restriction of Chemicals (REACH). 7.7 Halogen Free GR551x is compliant with BS EN 14582: 2007 in regards to halogens: fluorine, chlorine, bromine, and iodine content. Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

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