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Goodix GR5405 Hardware Design Manuallines

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GR5405 Hardware Design Guidelines
Version: 1.0
Release Date: 2024-09-27
Shenzhen Goodix Technology Co., Ltd.

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Summary of Contents for Goodix GR5405

  • Page 1 GR5405 Hardware Design Guidelines Version: 1.0 Release Date: 2024-09-27 Shenzhen Goodix Technology Co., Ltd.

  • Page 2: Trademarks And Permissions

    Copyright © 2024 Shenzhen Goodix Technology Co., Ltd. All rights reserved. Any excerption, backup, modification, translation, transmission or commercial use of this document or any portion of this document, in any form or by any means, without the prior written consent of Shenzhen Goodix Technology Co., Ltd. is prohibited.

  • Page 3: Preface

    Purpose This document presents the necessary circuit required for proper operation of GR5405 Bluetooth System-on-Chips (SoCs). Recommended chip interfaces, peripherals, schematic diagram, and PCB layout guidelines of the GR5405 SoCs are provided. This Hardware Design Guidelines intends to help system designers build minimal Bluetooth Low Energy (Bluetooth LE) hardware circuits and develop Bluetooth products.

  • Page 4: Table Of Contents

    2 Pinout................................. 2 2.1 QFN40.................................. 2 2.2 Pin Properties..............................4 2.2.1 PMU Pin Properties............................ 4 2.2.2 I/O Pin Properties............................5 3 Minimal Design for GR5405 SoC......................... 7 3.1 Schematic Design Guideline..........................7 3.1.1 Power Supply.............................. 7 3.1.1.1 Introduction............................7 3.1.1.2 Power-on Sequence........................... 9 3.1.1.3 I/O LDO.............................12...
  • Page 5 6.4 Rework Guideline.............................. 47 6.4.1 Component Removal..........................48 6.4.2 Site Redress...............................48 6.4.3 Solder Paste Printing..........................48 6.4.4 Component Placement..........................49 6.4.5 Component Attachment........................... 49 6.5 RoHS Compliant..............................49 6.6 SVHC Materials (REACH)............................49 6.7 Halogen Free..............................49 Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 6: Product Overview

    1 Product Overview The Goodix GR5405 is an automotive Bluetooth LE 5.3 SoC designed to operate across a wide temperature range, from –40°C to 105°C, and is AEC-Q100 Grade 2 certified. It is suitable for various automotive applications, including digital car key and Tire Pressure Monitoring System (TPMS).

  • Page 7: Pinout

    Table 2-1 Pin functions Voltage Pin # Pin Name Pin Type Description/Default Function Domain VSS_RF Analog/RF supply RF GND; connect to GND. RF_RX Analog/RF RF transceiver RX input RF_TX Analog/RF RF transceiver TX output Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
  • Page 8 Digital I/O Digital I/O supply input. VDDIO_1 Digital I/O supply Support external 2.3 V–3.6 V input voltage. AON_GPIO_2 Digital I/O Always-on GPIO, can wake up chip from sleep modes. AON_GPIO_3 Digital I/O Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 9: Pin Properties

    Table 2-2 PMU pin properties Pin Name Input/Output/GND Min. Typ. Max. Unit VDD_RF Input 1.15 1.21 VSS_RF VBAT_RF Input VIO_LDO_OUT Output CHIP_EN Input DIGCORE Output 1.03 1.05 VREG Output 1.13 1.15 1.21 Output VBATL Input Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 10: I/O Pin Properties

    Hi-Z MSIO_6 Hi-Z MSIO_5 Hi-Z MSIO_4 Hi-Z MSIO_3 Hi-Z MSIO_9 Hi-Z MSIO_8 Hi-Z AON_GPIO_0 AON_GPIO_1 AON_GPIO_2 AON_GPIO_3 AON_GPIO_4 AON_GPIO_5 AON_GPIO_6 AON_GPIO_7 GPIO_8 GPIO_9 Abbreviations mentioned above are listed in the table below: Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
  • Page 11 Default status after POR High level Low level Enabled Pull-up/Pull-down enable after POR Disabled Pull-up Pull-up/Pull-down selection after POR Pull-down Pin interrupt Fast capability is not supported. Fast capability Fast capability is supported. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 12: Minimal Design For Gr5405 Soc

    I/O pins • SWD interfaces To ensure the proper operation of a GR5405 SoC, the design guidelines for the schematic diagram and the PCB layout are illustrated in the following sections. 3.1 Schematic Design Guideline For the minimal schematic for a GR5405 SoC, see “Section 3.4 Reference...
  • Page 13 ANA_IO_LDO: Used to generate the I/O voltage to supply the pads of GR5405 and the external devices connecting to GR5405. It is also used to supply power to the stacked Flash. The bypass mode is enabled by default, and the output voltage is equal to VBATL.

  • Page 14: Power-On Sequence

    Do not power on VDDIO before VBATL. • When GR5405 works as Slave, VBATL cannot be powered on after CHIP_EN is pulled low. Otherwise, the I/O state might be out of control and forced to output high level. In GR5405 applications where devices are supplied by rechargeable batteries but the charger does not support power...
  • Page 15 ◦ When charging starts, V will instantly rise to the pre-set value, and GR5405 VBATL will also instantly reach the operating voltage or above. The system can keep working normally in this case, thanks to the delay circuit on CHIP_EN that helps ensure GR5405 power-on sequence.
  • Page 16 Vd = Vbat = 4.2 V (Max.) Vgs = Vg – Vs = 0.24 V Vsd (Min.) = Vs – Vd (Max.) = 0.1 V Recommended PMOS transistors and diodes are detailed as follows: Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 17: I/O Ldo

    3.1.1.3 I/O LDO The GR5405 has an on-chip linear LDO regulator that supplies always-on blocks, including always-on I/Os and digital logic blocks. Additionally, this regulator can supply external components (sensors) which interface to the GR5405. The LDO is capable of supplying up to 30 mA load current.

  • Page 18: Power Supply Scheme

    GR5405 internal Flash through a controllable switch. 3.1.1.4 Power Supply Scheme GR5405 SoCs are equipped with a complete set of power management modules which guarantee the smooth and secure functioning of the SoCs. This section introduces the reference circuit design (see the figure below).
  • Page 19 The capacitance of the pF capacitor can be adjusted to meet specific requirements for suppressing harmonics. The material selection is based on ensuring the minimum impedance at the positions where harmonic suppression is needed. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
  • Page 20 Ferrite bead, 1000 ohm @ 100 MHz, 350 1000 Ω @ Murata 0402 mA, 490 mohm, 0402 100 MHz BLM15AX102SZ1 Ferrite bead, 120 ohm @ 100 MHz, 200 120 Ω @ 100 Murata 0201 mA, 500 mohm, 0201 BLM03AG121SZ1 Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
  • Page 21 1.1 A 2.0 x 1.6 x 1.0 the AEC-Q200 AS1A2016102R2MT standard. Chilisin 0.19 Ω 400 mA 2.0 x 1.25 x 1.25 AKPB002012102R2M Scientic 0.41 Ω 1.05 A 1.75 x 1.05 x 1.0 SDHK1608HB2R2MTV01 Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 22: Clock

    3.1.2 Clock 3.1.2.1 Introduction GR5405 clock source is generated by an external 32 MHz crystal oscillator, and the real-time clock by an external 32.768 kHz crystal oscillator. 3.1.2.2 HFXO_32M The system clock, or CPU clock, is provided by an external 32 MHz crystal oscillator which connects to the XO_IN and XO_OUT pins of the SoC.

  • Page 23: Lfxo_32K

    MSIO_7. 3.1.2.3 LFXO_32K The GR5405 uses a low-power, low-frequency clock in sleep modes, which also extends battery lifespan. The utilization of the external 32.768 kHz crystal oscillator provides better accuracy, resulting in lower overall power consumption. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
  • Page 24 The GR5405 integrates an adjustable load capacitance, so that the external 32.768 kHz crystal oscillator can be directly connected to the RTC_IN and RTC_OUT pins of GR5405, and no external load capacitors are required.

  • Page 25: Introduction

    6 pF to 12.5 pF. 3.1.3 RF 3.1.3.1 Introduction GR5405 integrates a 2.4G RF transceiver, which operates based on the mechanisms described below: • On the receiver side: After the antenna receives an RF signal, the receiver digitizes the signal in a path: Low noise amplifier (LNA) >...

  • Page 26: Rf Scheme

    Note: • Choose a high-power amplifier (HPA) or a small-power amplifier (SPA) for GR5405 based on the transmission power needed. An HPA supports transmission power between -10 dBm and 15 dBm, whereas -20 dBm and 5 dBm is supported for an SPA.

  • Page 27: I/O Pins

    SoC matching network The PI type matching network (composed of the inductors L1, L2, and L3 plus capacitors C2, C3, C4, and C5) on the right transforms the PA output impedance of GR5405 to 50 ohm transmission line impedance. Note: The DC blocking capacitor (C1) that connects the two matching networks cannot be omitted.

  • Page 28: Swd Interfaces

    Input voltages of all I/Os and VIO_LDO_OUT/VDDIO_1 should not be higher than the VBATL voltage. 3.1.5 SWD Interfaces GR5405 connects to J-Link for debugging by using Serial Wire Debug (SWD) interfaces. The following table shows the pins to which the SWD interfaces connect.

  • Page 29: Components Layout

    When designing the layout, make sure the GR5405 SoC is placed as close to the antenna interface as possible, and no other traces or components are under the RF routing if possible (the layout and routing of RF components are of higher priority).

  • Page 30: Rf Input Power Supply

    In case the capacitors are not placed on the same layer with the chip, they can be connected through vias, and the vias should be located close to the decoupling capacitors. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 31: Clock

    By taking 4-layer PCB as an example, if the ground below the crystal is clean and no crosstalk or interference is involved, provide openings underneath the crystal pads (as shown in Figure 3-17) to reduce parasitic capacitance. Figure 3-16 Reference clock layout Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 32: Rf Port

    Components in this matching network should be placed as close to the RF pins (RF_RX and RF_TX) as possible. Try to place the first component no further than 1 mm from the RF pin. Figure 3-18 shows the PCB layout of the RF port. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 33: Rse Certificate Recommendations

    Ground vias should be placed along the transmission line every 1.25 mm and right next to the ground pads of the matching components. In addition, the antenna matching components should be placed close to the antenna feedpoint. 3.2.6 RSE Certificate Recommendations Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
  • Page 34 ① ② ③ ④ Figure 3-19 RF radiation sources from GR5405 To enhance RF performance and minimize PCB radiation, follow the layout and routing recommendations on RF port below: • Placing RF matching components on the same line with RF_TX is of high priority, as shown in the blue box in Figure 3-18.

  • Page 35: Esd Protection Design

    System efficient electrostatic discharge (ESD) design is crucial for any circuits, and requires users to follow the design guidelines (including schematic diagrams, PCB layout, and product structural designs) provided in the sections below. 3.3.1.1 ESD Schematic Design GR5405 SoC is powered by an independent external LDO regulator (see “Section 3.1.1 Power Supply” for details).

  • Page 36: Pcb Layout Design

    • It is recommended to use PCB with four layers or above, and place GR5405 SoC on the layer adjacent to the GND layer. Make sure the GND layer is solid and complete, to effectively prevent static from setting in.
  • Page 37 Those signals should also be wrapped with ground traces. Place decoupling capacitors as close to the power pins of GR5405 as possible, to keep the power return path the shortest, so as to enhance filtering performance.
  • Page 38 It is recommended to wrap the I/O pins and ESD susceptible signals with GND traces. Figure 3-23 Improper I/O routing at board edge (not shielded by GND traces) Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
  • Page 39 PCB roung through pad of filter capacitor Figure 3-25 Proper routing for a capacitor (as an example) Connecng to filter capacitor with long wires Figure 3-26 Improper routing for a capacitor (as an example) Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 40: Product Structural Design

    Use an antistatic bag/tray to hold the SoC. • Countermeasures against ESD are essential for soldering irons, welding tables, and test instruments. • Strictly comply with ESD preventive requirements for the production line during production and transport. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 41: Reference Design

    3.4 Reference Design The reference schematic is shown below. Figure 3-27 Reference schematic for GR5405 QFN40 Note: For the reference schematic of GR5405, see the corresponding reference design in the GR5405 Reference Design package. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 42: Faq

    In designing a PCB, can I modify the recommended RF matching circuit layout due to limited space? • Issue Analysis GR5405 recommends two matching circuits for RF: a matching circuit close to GR5405 and a matching circuit close to the antenna. Whether these two matching circuits can be simplified or removed needs to be treated differently.

  • Page 43: Glossary

    QSPI Queued Serial Peripheral Interface RoHS Restriction of Hazardous Substances Directive System-in-Package SNSADC Sense Analog-to-digital Converter System-on-Chip Serial Peripheral Interface SVHC Substance of Very High Concern Serial Wire Debug Glass Transition Temperature Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
  • Page 44 Glossary Name Description TPMS Tire Pressure Monitoring System Universal Serial Bus UART Universal Asynchronous Receiver/Transmitter Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 45: Appendix: Assembly Guideline

    Connecting Electronics Industries (IPC) is used here for designing PCB pad pattern. However, because of exposed die paddle and the package lands on the bottom side of the package of GR5405, certain constraints are added to IPC’s methodology. The pad pattern developed here includes considerations for lead and package tolerances.
  • Page 46 QFN Pad Count Total Thickness 0.75 ± 0.05 mm QFN Pad Pitch 0.50 Pad Width 0.25 Exposed Pad Size 4.5 x 4.5 ± 0.01 mm The figure below shows the wettable QFN40 package outlines. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
  • Page 47 Drawing is not to scale. Table 6-2 Wettable QFN40 package dimensions Dimensions in mm Parameter Symbol Min. Nom. Max. Total thickness 0.700 0.750 0.800 Stand off 0.000 0.020 0.050 Mold thickness 0.550 Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 48: Board Mounting Guideline

    This is typically accomplished by considering the following two ratios: • Area ratio = area of aperture opening/aperture wall area Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 49: Via Types And Solder Voiding

    QFN packages. Nitrogen purge is also recommended during reflow. The most common surface finishes that are compatible with lead-free surface mount technology (SMT) process are: • Organic solderability preservatives (OSP) • Electroless nickel/Immersion gold (ENIG) Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 50: Pcb Materials

    Placement With the self-aligning characteristic of the QFN packages during reflow, the placement accuracy is < 30% of the pad width or as long as the solder pads can touch solder paste. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 51: Smt Reflow Process

    6-3. Figure 6-4 JEDEC recommended lead-free reflow profile The GR5405 fulfills the lead-free soldering requirements from IPC/JEDEC, i.e. reflow soldering with a peak temperature up to 260°C. The lead frame is made of CμAg and has Matte Sn plating. This is 100% Sn and thus Pb-free. Plating thickness is 300 –...

  • Page 52: Rework Guideline

    In most applications, QFN packages will be mounted on smaller, thinner, and denser PCBs that introduce further challenges due to handling and heating issues. Because reflow of adjacent parts is not desirable during rework, the Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

  • Page 53: Component Removal

    Because of the small size of GR5405 SoCs, the vacuum pressure should be kept below 15 inch of Hg. This will allow the component not to be lifted out if all joints have not been reflowed and avoid the pad lift-off.

  • Page 54: Component Placement

    GR5405 is RoHS compliant, as per Directive 2002/95/EC and its subsequent amendments. 6.6 SVHC Materials (REACH) GR5405 is compliant with Substance of Very High Concern (SVHC) list based on the publication by European Chemicals Agency (ECHA) on October 28, 2008 Regulation (EC) No 1907/2006 concerning Registration, Evaluation, Authorisation and Restriction of Chemicals (REACH).

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