Goodix GR533 Series Hardware Design Manuallines

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GR533x Hardware Design Guidelines

Version: 1.3

Release Date: 2024-06-06

Shenzhen Goodix Technology Co., Ltd.

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Page 1 GR533x Hardware Design Guidelines Version: 1.3 Release Date: 2024-06-06 Shenzhen Goodix Technology Co., Ltd.
Page 2: Trademarks And Permissions
Copyright © 2024 Shenzhen Goodix Technology Co., Ltd. All rights reserved. Any excerption, backup, modification, translation, transmission or commercial use of this document or any portion of this document, in any form or by any means, without the prior written consent of Shenzhen Goodix Technology Co., Ltd. is prohibited.
Page 3: Preface
• Added selection descriptions for the ferrite bead on the VDD_RF pin and updated the recommended bead model. • Updated the reference design schematics. 2024-06-06 • Updated the recommended design for charger without PPM. • Updated selection of the 2.2 μH inductor. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 4: Table Of Contents
3.2.3 Power Supply............................32 3.2.3.1 DC-DC Switching Regulator......................32 3.2.3.2 RF Input Power Supply........................33 3.2.4 Clock................................34 3.2.5 RF Port..............................35 3.2.6 RSE Certificate Recommendations......................36 3.3 ESD Protection Design............................38 3.3.1 System-level ESD Design........................... 38 Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 5 6.4 Rework Guideline.............................. 57 6.4.1 Component Removal..........................58 6.4.2 Site Redress...............................58 6.4.3 Solder Paste Printing..........................58 6.4.4 Component Placement..........................59 6.4.5 Component Attachment........................... 59 6.5 RoHS Compliant..............................59 6.6 SVHC Materials (REACH)............................59 6.7 Halogen Free..............................59 Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 6: Product Overview
Product Overview 1 Product Overview The Goodix GR533x series is a Bluetooth Low Energy (Bluetooth LE) 5.3 System-on-Chip (SoC), suitable for IoT applications, supporting Bluetooth mesh networking protocols. ® ® Based on Arm Cortex -M4F CPU core running at 64 MHz, the GR533x integrates a 2.4 GHz RF transceiver, Bluetooth LE 5.3 protocol stack, 512 KB on-chip Flash memory, 96 KB system SRAM, and a rich set of peripherals.
Page 7 2 x UART modules up to 2 Mbps with flow control and IrDA features ◦ 2 x I2C modules for peripheral communication, up to 1 MHz, operating as either Master or Slave Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 8 Ultra deep sleep mode: 2.2 µA (Typical), with no memory data in retention and wakeup sources from SLP Timer or AON I/Os ◦ OFF mode: 200 nA (Typical), with system in reset mode • Operating temperature range ◦ GR5331: -40°C to 85°C ◦ GR5332: -40°C to 105°C • Packages Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 9: Block Diagram
• Power Management Unit (PMU) subsystem ◦ Power supply for the whole SoC, including internal modules and external peripherals ◦ Efficient and reliable SoC power management • Clock Generation Unit (CGU) subsystem Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 10: Applications
• Health and medical applications ◦ Thermometer ◦ SpO2 meter ◦ Blood glucose and pressure meter ◦ Weight scale • Bluetooth HID devices ◦ Remote control ◦ Gaming controller ◦ Stylus pen Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 11: Pinout
Input of RF supply; connect to VREG. VSS_RF Analog/RF supply RF GND; connect to GND. RF_RX Analog/RF RF transceiver RX input RF_TX Analog/RF RF transceiver TX output PA_GND Analog/RF Supply RF PA GND; connect to ground. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 12 Always-on GPIO, can wake up chip from sleep modes AON_GPIO_5 Digital I/O AON_GPIO_6 Digital I/O Input pin, used for factory test mode selection Analog/RF • 1: factory test mode • 0: normal operation mode Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 13: Qfn48
GR533x QFN48 GPIO_1 MSIO_8 GPIO_2 MISO_9 GPIO_3 MISO_0 GPIO_4 MSIO_1 GPIO_5 MSIO_2 GPIO_6 MSIO_3 RF pin Digital I/O & supply pin Power pin Analog IO pin Figure 2-2 QFN48 device pinout (top view) Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 14 Mixed Signal I/O MSIO_4 Mixed Signal I/O VBATL MSIO_3 Mixed Signal I/O Configurable mixed-signal I/O with digital GPIO and SNSADC MSIO_2 Mixed Signal I/O MSIO_1 Mixed Signal I/O MSIO_0 Mixed Signal I/O Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 15: Pin Properties
Note: The pad drive strength for all I/Os (including GPIOs/ AON_GPIOs/ MSIOs) can be configured to 2 mA/4 mA/8 mA/12 mA under 3.3 V voltage. 2.3 Pin Properties 2.3.1 PMU Pin Properties Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 16: I/O Pin Properties
Pin Interrupt Chip Wake-up Fast Capability After POR After POR After POR GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 MSIO_7 Hi-Z MSIO_6 Hi-Z MSIO_5 Hi-Z MSIO_4 Hi-Z MSIO_3 Hi-Z MSIO_2 Hi-Z Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 17 Hi-Z High impedance Default status after POR High level Low level Enabled Pull-up/Pull-down enable after POR Disabled Pull-up Pull-up/Pull-down selection after POR Pull-down Pin interrupt Fast capability Fast capability is not supported. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 19: Minimal Design For Gr533X Soc
For the minimal schematic for a GR533x SoC, see “Section 3.4 Reference Design”. 3.1.1 Power Supply 3.1.1.1 Introduction GR533x SoCs are powered by external power sources through VBATL (voltage range: 2.0 V to 3.63 V). Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 20 VDDIO1: supply for I/O1 group; from external power voltage or VIO_LDO_OUT. • MSIO_7: input 2.5 V external voltage to burn eFuse. By burning the eFuse configuration, you can disable the SWD debugging function that is multiplexed by GPIO_0/GPIO_1. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 21: Power-On Sequence
To avoid this problem, it is recommended to follow the charger solutions below: • Using a charger with PPM To use a charger that supports system power path management, follow the recommended circuit design in Figure 3-3. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 22 In uncharged state, the battery conducts through the body diode of the PMOS transistor (Q1) to the LDO input (Vin pin), providing a high voltage to the source voltage (Vs) of Q1. By setting the gate voltage (Vg) Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 23 Vd = Vbat = 4.2 V (Max.) Vgs = Vg – Vs = 0.24 V Vsd (Min.) = Vs – Vd (Max.) = 0.1 V Recommended PMOS transistors and diodes are detailed as follows: Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 24: I/O Ldo
I/O domain MSIO, corresponding to reference voltage levels at VDDIO_0, VDDIO_1, and VBATL respectively. Figure 3-7 is a circuit diagram showing the connection between VIO_LDO_OUT and the I/O domains. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 25: Power Supply Scheme
GR533x SoCs are equipped with a complete set of power management modules which guarantee the smooth and secure functioning of the SoCs. This section introduces the reference circuit design by taking a GR5332 SoC in QFN48 package as an example (see the figure below). Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 26 The capacitance of the pF capacitor can be adjusted to meet specific requirements for suppressing harmonics. The material selection is based on ensuring the minimum impedance at the positions where harmonic suppression is needed. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 27 CAP, CER, 0.1 µF, 20%, X6S, 0201, 10 V, Murata 0.1 μF 0201 -55°C to +105°C GRM033C81C104ME14 Ferrite bead, 1000 ohm @ 100 MHz, Murata 1000 Ω @ 100 MHz 0201 200 mA, 1.25 mohm BLM03AX102SN1 Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 28 1.6 x 0.8 x 0.8 MPH160809S2R2 2.2 µH ± 20% Murata 0.38 Ω 300 mA 1.6 x 0.8 x 0.8 LQM18PN2R2MFH Scientic 0.41 Ω 1.05 A 1.75 x 1.05 x 1.0 SDHK1608HB2R2MT Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 29: Clock
Table 3-6 32 MHz crystal specifications Parameter Description Min. Typ. Max. Unit Crystal Freq Crystal oscillator frequency Equivalent series resistance Load capacitance load f-Xtal Crystal frequency initial tolerance ±50 Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 30: Lfxo_32K
The GR533x integrates an adjustable load capacitance, so that the external 32.768 kHz crystal oscillator can be directly connected to the RTC_IN and RTC_OUT pins of GR533x, and no external load capacitors are required. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 31: Introduction
To ensure system stability and XO accuracy, load capacitance of the 32.768 kHz crystal oscillator should be within the range from 6 pF to 12.5 pF. 3.1.3 RF 3.1.3.1 Introduction GR533x integrates a 2.4G RF transceiver, which operates based on the mechanisms described below: Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 32 VBAT_RF Main Band Gap VDD_RF VDD_AMS VDD_VCO Class D HFXO_32M CLK Gen Class AB Balun RF_TX Buﬀer SXPLL RF_RX Mixer Power Domain: VBAT_RF VDD_AMS VDD_RF VDD_VCO Figure 3-11 GR5332 transceiver block diagram Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 33: Rf Scheme
For detailed information about RF PA selection and matching circuit for GR533x, see GR533x RF PA Application Note. 3.1.3.2 RF Scheme The following figure is the recommended RF matching circuit in the GR533x SoC minimal system. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 34 CAP, CER, 2.0 pF (±0.1 pF), NPO, 0201, 50 V, -55°C to 2.0 pF 0201 Murata GRM0335C1H2R0BA01 +125°C CAP, CER, 2.5 pF (±0.1 pF), NPO, 0201, 50 V, -55°C to 2.5 pF 0201 Murata GRM0335C1H2R5BA01 +125°C Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 35: I/O Pins
3.1.5 SWD Interfaces GR533x connects to J-Link for debugging by using Serial Wire Debug (SWD) interfaces. The following table shows the pins to which the SWD interfaces connect in QFN48 and QFN32 packages. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 36: Pcb Design And Layout Guideline
All components operating at high frequency should have their layout made as compact as possible. This will prevent the cross-coupling between lines and also minimize the parasitic effects which will have a negative impact on the operating parameters. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 37: Power Supply
The power trace of VREG should go through the DC-DC output capacitor (C16) first before being connected to VREG. For devices in QFN48 package, it is recommended to connect the VSS_BUCK pin to the E-PAD through vias. Avoid connecting them on the same layer. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 38: Rf Input Power Supply
The power trace should be as short as possible, and at least 0.2 mm wide. A minimum distance at 0.2 mm from other signals should be guaranteed. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 39: Clock
By taking 4-layer PCB as an example, if the ground below the crystal is clean and no crosstalk or interference is involved, provide openings underneath the crystal pads (as shown in Figure 3-19) to reduce parasitic capacitance. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 40: Rf Port
Components in this matching network should be placed as close to the RF pins (RF_RX and RF_TX) as possible. Try to place the first component no further than 1 mm from the RF pin. Figure 3-20 shows the PCB layout of the RF port. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 41: Rse Certificate Recommendations
3.2.6 RSE Certificate Recommendations Board-level RF radiation might cause an SoC to fail in passing FCC RSE certificate. Such radiation comes from various sources, including SoC package, wafer, PCB circuit path (major source), and antenna. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 42 Avoid connecting the VREG network to the VDD_RF pin by routing through the RF routing reference layer. Instead, it is recommended to pass through the E-PAD projection area, as shown in Figure 3-17. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 43: Esd Protection Design
System efficient electrostatic discharge (ESD) design is crucial for any circuits, and requires users to follow the design guidelines (including schematic diagrams, PCB layout, and product structural designs) provided in the sections below. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 44: Esd Schematic Design
Maximum DC resistance 230 mΩ Table 3-14 Recommended TVS diodes Operating (V) V (kV) Part Number Package Manufacturer clamp Temperature AZ5C25-01B –55°C to 85°C • Contact discharge: ±13 kV 0201 Amazing Micro. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 45: Pcb Layout Design
It is not recommended to place charging pads (CHAR+ and CHAR-) and GR533x SoC on the same layer. However, if the charging pads and GR533x SoC are on the same layer, the spacing between the charging pads and the SoC should be at least 4 mm. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 46 ESD susceptibility of I/O pins. Avoid routing signals susceptible to ESD events (such as clocks and reset pins) at the edge of the board. It is recommended to wrap the I/O pins and ESD susceptible signals with GND traces. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 47 The capacitors or ESD protection devices should be routed through the pad. Avoid using long traces to connect the capacitors/ESD protection devices to pad, which undermines filtering/protection performance. PCB roung through pad of ﬁlter capacitor Figure 3-28 Proper routing for a capacitor (as an example) Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 48: Product Structural Design
Use an antistatic bag/tray to hold the SoC. • Countermeasures against ESD are essential for soldering irons, welding tables, and test instruments. • Strictly comply with ESD preventive requirements for the production line during production and transport. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 49: Reference Design
Taking GR5332CENE in QFN48 package as an example, the reference schematic is shown below. Figure 3-30 Reference schematic for GR5332CENE QFN48 Note: For the reference schematic specific to each part number of GR533x, see the corresponding reference design in the GR533x Reference Design package. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 50: Faq
S11 parameter or the Smith chart from the vector network analyzer. However, for matching of other indicators (such as antenna gain and directionality), you are recommended to seek help from professional antenna factories. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 51: Glossary
QSPI Queued Serial Peripheral Interface RoHS Restriction of Hazardous Substances Directive System-in-Package SNSADC Sense Analog-to-digital Converter System-on-Chip Serial Peripheral Interface SVHC Substance of Very High Concern Serial Wire Debug Glass Transition Temperature Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 53: Appendix: Assembly Guideline
GR533x, certain constraints are added to IPC’s methodology. The pad pattern developed here includes considerations for lead and package tolerances. 6.1 Package Information This section provides comprehensive details on mechanical packaging information. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 54: Qfn32
±0.05 mm QFN Pad Count Total Thickness 0.75 ±0.05 mm QFN Pad Pitch Pad Width ±0.05 mm Exposed Pad Size 2.8 x 2.8 ±0.1 mm The figure below shows the QFN32 package outlines. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 55 Dimensions in inch Symbol Min. Nom. Max. Min. Nom. Max. 0.700 0.750 0.800 0.028 0.030 0.031 0.000 0.020 0.050 0.000 0.001 0.002 0.550 0.022 0.203 REF. 0.008 REF. 0.150 0.200 0.250 0.006 0.008 0.010 Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 56: Qfn48
QFN Pad Count Total Thickness 0.75 ± 0.05 mm QFN Pad Pitch 0.40 Pad Width 0.20 Exposed Pad Size 4.6 x 4.6 ± 0.01 mm The figure below shows the QFN48 package outlines. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 57 Table 6-4 QFN48 package dimensions Dimensions in mm Dimensions in inch Symbol Min. Nom. Max. Min. Nom. Max. 0.700 0.750 0.800 0.028 0.030 0.031 0.000 0.020 0.050 0.000 0.001 0.002 0.550 0.022 Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 58: Board Mounting Guideline
This is typically accomplished by considering the following two ratios: • Area ratio = area of aperture opening/aperture wall area Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 59: Via Types And Solder Voiding
QFN packages. Nitrogen purge is also recommended during reflow. The most common surface finishes that are compatible with lead-free surface mount technology (SMT) process are: • Organic solderability preservatives (OSP) • Electroless nickel/Immersion gold (ENIG) Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 60: Pcb Materials
Placement With the self-aligning characteristic of the QFN packages during reflow, the placement accuracy is < 30% of the pad width or as long as the solder pads can touch solder paste. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 61: Smt Reflow Process
300 – 600 µin. The Matte Sn CμAg LF can withstand 3x reflow at 260°C. Table 6-5 Reflow profile parameters Profile Parameters Lead-Free Assembly, Convection, IR/Convection Ramp-up rate (Tsmax to Tp) 3°C/second (max) Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 62: Rework Guideline
In most applications, QFN packages will be mounted on smaller, thinner, and denser PCBs that introduce further challenges due to handling and heating issues. Because reflow of adjacent parts is not desirable during rework, the Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 63: Component Removal
The solvent is usually specific to the type of paste used in the original assembly and paste manufacturer’s recommendations should be followed. 6.4.3 Solder Paste Printing Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.
Page 64: Component Placement
Agency (ECHA) on October 28, 2008 Regulation (EC) No 1907/2006 concerning Registration, Evaluation, Authorisation and Restriction of Chemicals (REACH). 6.7 Halogen Free GR533x is compliant with BS EN 14582: 2007 in regards to halogens: fluorine, chlorine, bromine, and iodine content. Copyright © 2024 Shenzhen Goodix Technology Co., Ltd.

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