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Goodix GR551 Series Hardware Design Manuallines

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GR551x Hardware Design Guidelines
Version: 2.5
Release Date: 2023-04-20
Shenzhen Goodix Technology Co., Ltd.

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Summary of Contents for Goodix GR551 Series

  • Page 1 GR551x Hardware Design Guidelines Version: 2.5 Release Date: 2023-04-20 Shenzhen Goodix Technology Co., Ltd.
  • Page 2 Copyright © 2023 Shenzhen Goodix Technology Co., Ltd. All rights reserved. Any excerption, backup, modification, translation, transmission or commercial use of this document or any portion of this document, in any form or by any means, without the prior written consent of Shenzhen Goodix Technology Co., Ltd. is prohibited.

  • Page 3: Preface

    “Two-layer PCBs in QFN56”. Introduced the GR5515I0ND SoC: • Added “GR5515I0ND” for pinout details; 2020-08-30 • Added “External Flash” for recommended external Flash for GR5515I0ND; • Added the reference schematic for GR5515I0ND in “Reference Design”; Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 4 • Updated the GR5515RGBD status from "NRND" to "Active". • Added a note for classifying GR5513BEND as "NRND". • Updated “Features” of GR551x overview and “Introduction” of power supply. 2023-04-20 • Added “Power-on Sequence”. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 5: Table Of Contents

    3.2.3 Power Supply............................37 3.2.3.1 DC-DC Switching Regulator......................37 3.2.3.2 RF Input Power Supply........................38 3.2.4 Clock................................39 3.2.5 RFIO Port..............................40 3.2.6 Grounding..............................41 3.2.7 ESD Protection Design..........................42 3.2.7.1 System-level ESD Design........................42 Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 6 7.4 Rework Guideline.............................. 77 7.4.1 Component Removal..........................78 7.4.2 Site Redress...............................78 7.4.3 Solder Paste Printing..........................78 7.4.4 Component Placement..........................79 7.4.5 Component Attachment........................... 79 7.5 RoHS Compliant..............................79 7.6 SVHC Materials (REACH)............................79 7.7 Halogen Free..............................79 Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 7: Gr551X Overview

    1 GR551x Overview The Goodix GR551x family is a single-mode, low-power Bluetooth 5.1 System-on-Chip (SoC). It can be configured as a Broadcaster, an Observer, a Central, or a Peripheral and supports the combination of all the above roles, making it an ideal choice for Internet of Things (IoT) and smart wearable devices.
  • Page 8 1x SPI master interface and 1 x SPI slave interface for host communication, up to 32 MHz ◦ 2 x I2S interfaces (1 I2S master interface + 1 I2S slave interface) ◦ ISO 7816 interface • Security ◦ Complete secure computing engine: AES 128-bit/192-bit/256-bit symmetric encryption (ECB, CBC) Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 9 I/O voltage: 1.8 V to 3.3 V (Typical) (for GR5515I0NDA/GR5515IENDU/GR5513BENDU Flash using high voltage, the VIO_LDO_OUT shall be connected to VBATL in schematic circuit.) • Low-power consumption modes ◦ Deep sleep mode: 2.7 µA (Typical), with full 256 KB SRAM retention Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 10: Block Diagram

    AON SLP AON RTC CPLL_192M LFRC_32K LP Comp. Timer Timer PMU Subsystem MCU Subsystem Figure 1-1 GR551x block diagram Note: For more details of each module in this block diagram, see GR551x Datasheet. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 11: Pinout

    GPIO_7 MSIO2 GPIO_8 MSIO3 GPIO_9 MSIO4 GPIO_10 RTC_OUT Digital I/O & supplies pin Analog pin RF pin Figure 2-1 GR5515IGND/GR5515IENDU QFN56 package pinout Table 2-1 shows pin descriptions of GR5515IGND/GR5515IENDU QFN56 package. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 12 When GR5515IENDU is used and the Flash is Connected internally VIO_LDO_OUT supplied at a high voltage, the pin is used as the to VDDIO0 power input pin of VDDIO0 digital I/O domain by being connected to VBATL Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 13 AON_GPIO_7 Digital I/O Always-on GPIO VDDIO0 GPIO_24 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO0 GPIO_25 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO0 Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 14: Gr5515I0Nda Qfn56

    2.2 GR5515I0NDA QFN56 Figure 2-2 shows the pin assignments of GR5515I0NDA QFN56 package (top view). The pins (Pin 43 to Pin 53) of GR5515I0NDA QFN56 package are different from those of GR5515IGND/GR5515IENDU QFN56 package. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 15 Pin Name Pin Type Description/Default Function Voltage Domain Synthesizer VCO supply/RF supply: 1.1 V; connect to VDD_VCO/VDD_RF Analog/RF supply VREG. Analog/RF RX input and TX output VBATT_RF Analog/RF Supply Connect to VBATL. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 16 On-chip LDO output for digital core. Connect to a 1 µF VDD_DIGCORE_1V capacitor. VREG Feedback pin from switching regulator DC-DC converter switching node VSS_BUCK DC-DC converter supply and general battery GND VBATL Power supply: 2.2 V to 3.8 V Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 17 General purpose I/O; pad drive level is 2 mA. VDDIO0 GPIO_16 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO0 GPIO_30 Digital I/O General purpose I/O; pad drive level is 2 mA. VDDIO0 Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 18: Gr5515Rgbd Bga68

    Output of inverting amplifier connected to 32 MHz XO_OUT Analog/RF crystal Input of inverting amplifier connected to 32 MHz XO_IN Analog/RF crystal 2.3 GR5515RGBD BGA68 Figure 2-3 shows the pin assignments of GR5515RGBD BGA68 package (top view). Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 19 Table 2-3 GR5515RGBD BGA68 package pin descriptions Pin # Pin Name Pin Type Description/Default Function Voltage Domain VDD_VCO Analog/RF supply Synthesizer VCO supply: 1.1 V; connect to VREG Analog/RF Test Mux +output Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 20 General purpose I/O; default: SWD_IO; pad drive level GPIO1 Digital I/O VDDIO1 is 2 mA. DGND Digital GND Digital Ground DGND Digital GND Digital Ground AON_GPIO1 Digital I/O Always-on GPIO; pad drive level is 2 mA. VDDIO0 Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 21 Connected internally VIO_LDO_OUT Analog/PMU Output of On-Chip I/O supply regulator. to VDDIO0 Configurable to be a GPIO mixed signal (SNSADC MSIO0 Mixed Signal I/O VBATL interface); pad drive level is 2 mA. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 22: Gr5515Ggbd Bga55

    Output of inverting amplifier connected to 32.768 kHz RTC_OUT Analog/PMU crystal AON_GPIO2 Digital I/O Always-on GPIO; pad drive level is 2 mA. VDDIO0 2.4 GR5515GGBD BGA55 Figure 2-4 shows the pin assignments of GR5515GGBD BGA55 package (top view). Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 23 Pin Type Description/Default Function Voltage Domain VDD_RF Analog/RF supply RF supply: 1.1 V VDD_VCO Analog/RF supply Synthesizer VCO supply; connect to VREG Input of inverting amplifier connected to 32 MHz XO_IN Analog/RF crystal Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 24 MSIO2 Mixed Signal I/O VBATL interface); pad drive level is 2 mA. Configurable to be a GPIO mixed signal (SNSADC MSIO0 Mixed Signal I/O VBATL interface); pad drive level is 2 mA. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 25 Always-on GPIO; pad drive level is 2 mA. VDDIO0 VBATL Analog/PMU Power supply: 2.2 V to 3.8 V VREG Analog/PMU Feedback pin of switch regulator Analog/PMU DC-DC converter switching node PMUGND Analog/PMU DC-DC converter & general battery GND pin Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 26: Gr5513Bend (Nrnd)/Gr5513Bendu Qfn40

    VDD_VCO/VDD_RF Analog/RF supply connect to VREG. Analog/RF RX input and TX output VBATT_RF Analog/RF Connect to VBATL. General purpose I/O; default: SWD_CLK; pad GPIO_0 Digital I/O VDDIO1 drive level is 2 mA. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 27 2 mA. Configurable to be a GPIO mixed signal (SNSADC MSIO0 Mixed Signal I/O VBATL interface); pad drive level is 2 mA. TEST_MODE Digital I/O Factory test mode selection pin VDDIO0 Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 28 AMS supply 1.1 V; connect to VREG. Output of inverting amplifier connected to 32 XO_OUT Analog/RF MHz crystal Input of inverting amplifier connected to 32 MHz XO_IN Analog/RF crystal Analog/RF Test Mux + output Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 29: Minimal Design For Gr551X Soc

    Low Power DC-DC Digital LDO Control Switch Stacked Flash Always ON Power Power Power Power Island VDDIO Island #n Island #1 Power Island #1 Island #1 Figure 3-1 Power management block diagram Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 30: Power-On Sequence

    To avoid this problem, it is recommended to follow the charger solutions below: Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 31 EN pin of LDO (V ) equals Vbat; at this point, LDO is enabled, and LDO_EN GR551x can be started normally. During charging, the relations between Q1 state and V are as follows: LDO_EN Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 32: Power Supply Scheme

    > –0.45 V (Typ.) 520 mΩ SOT-723 Semiconductor Alternatively, you can also add an external circuit that enables path management for the charger, so that GR551x can be started normally. 3.1.1.3 Power Supply Scheme Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 33 • VDD_MCU_CORE: connected to the power of the digital core internally. The pin is left unconnected externally by • default. It is only relevant to BGA68 package. VBATT_RF: connected to VBATL • Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 34 CAP CER NPO ±5% 50 V 15 pF 0603 04025A150JAT2A FB1, FB2 Ferrite Bead, 120 Ω @ 100 MHz, 120 Ω @ 100 MHz 0603 Murata 400 mA, 500 mohm, 0603 BLM18AG121SN1 Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 35: I/O Ldo

    I/O domain MSIO, corresponding to reference voltage levels at VDDIO0, VDDIO1, and VBATL respectively. Note that VDDIO0 is connected to VIO_LDO_OUT internally, and is not bonded to any package pins. Figure 3-6 is a circuit diagram showing the connection between VIO_LDO_OUT and the I/O domains. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 36 I/O LDO is set to off mode automatically based on eFuse configurations after system startup. • Use VIO_LDO_OUT as input for the VDDIO0 domain, and connect VIO_LDO_OUT to the external power supply of 3.3 V or VBATL. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 37: Clock

    -40°C to +85°C -40°C to +85°C Size (L x W x H, mm) 2.5 x 2.0 x 0.60 2.5 x 2.0 x 0.60 2.0 x 1.6 x 0.60 2.5 x 2.0 x 0.60 Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 38: Khz Clock

    Initial tolerance +/–20 ppm Tolerance over Temp. +/–250 ppm Load capacitance 9 pF 90,000 ohm Temperature range –40°C to +85°C Size (L x W x H, mm) 1.6 x 1.0 x 0.50 Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 39: Introduction

    The modulated carrier wave is delivered to a power amplifier (PA) with amplification factor configurable by the digital gain settings. The modulated carrier is transmitted to the antenna through a low-power or high-power PA path. The antenna radiates the amplified carrier wave through electromagnetic waves. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 40: Rf Scheme

    When configured to GPIOs, they can be set as input, output, with configurable pull-up or pull-down resistors. I/O pins retain their last state when system enters the sleep or deep sleep mode. Only AON_GPIOs can be used to wake up the system from sleep/deep sleep mode. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 41: Swd Interfaces

    GR5515I0NDA uses an external Flash with various model options provided. GR5515I0NDA supports both low-voltage (typical: 1.8 V) and high-voltage (typical: 3.3 V) Flash. According to the electrical characteristics and functional requirements of the SoCs, Goodix recommends the following GR5515I0NDA Flash candidates. Table 3-11 Recommended GR5515I0NDA Flash candidates (high voltage)

  • Page 42: Pcb Design And Layout Guideline

    L2: internal ground plane layer, used for both the ground return path and the reference plane for the 50 ohm RF transmission line L3: internal power layer, used to split power domains and place a small number of signal lines L4: bottom layer where components and signal lines are placed Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 43: Components Layout

    GND pin as possible. It is recommended to connect the C15 GND pin to VSS_BUCK by using GND Polygon Plane, so that the return path of the power can be kept minimal. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 44: Rf Input Power Supply

    The power trace should be as short as possible, and at least 0.2 mm wide. A minimum distance at 0.2 mm from other signals should be guaranteed. D<3mm D<3mm D<3mm D<3mm Figure 3-11 Reference layout and routing for RF input power supply Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 45: Clock

    It is recommended to shield the routes of the 32 MHz crystal. If the ground below the crystal is clean and no crosstalk or interference is involved, provide openings on the pad underneath the crystal (as shown in Figure 3-14), which helps to reduce parasitic capacitance. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 46: Rfio Port

    Components in this network must be placed as close as possible to the RFIO pin. Try to place the first component no further than 1 mm from the RFIO pin. Figure 3-15 shows the PCB layout of the RF port. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 47: Grounding

    Always provide a solid grounding for the radio IC of GR551x. Use as many vias as possible to create a solid GND under the IC itself and connect it to inner and bottom GND layers. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 48: Esd Protection Design

    CHAR- FB1=600 Ω BLM15PX601SN1 Figure 3-16 ESD protection scheme at charging pads Recommended models of TVS diodes and ferrite beads, as well as model selection requirements, are listed in the tables below. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 49 If an external WDT needs to be included, do not start the WDT before firmware is programmed to the SoC, to avoid inadvertent system reset. Choose WDT that meets the requirements in Table 3-17. A recommended model series is also provided. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 50: Pcb Layout Design

    R1 10K CHIP_EN nRESET R2 10K WDI_820 SGM820 GR551x GPIO nWDO Figure 3-17 Hardware WDT schematic design (reference) 3.2.7.1.2 PCB Layout Design Live by the following rules for GR551x PCB grounding: Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 51 ESD susceptibility of I/O pins. Avoid routing signals susceptible to ESD events (such as clocks and reset pins) at the edge of the board. It is recommended to shield the I/O pins and ESD susceptible signals with GND traces. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 52 The capacitors or ESD protection devices should be routed through the pad. Using long wires to connect the capacitors/ESD protection devices to pad undermines filtering/protection performance, and is therefore not recommended. PCB roung through pad of filter capacitor Figure 3-21 Proper routing for a capacitor (as an example) Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 53: Product Structural Design

    Use an antistatic bag/tray to hold the SoC. • Countermeasures against ESD are essential for soldering irons, welding tables, and test instruments. • Strictly comply with ESD preventive requirements for the production line during production and transport. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 54: Reference Design

    Reference Design 4 Reference Design 4.1 Reference Schematic Diagram Figure 4-1 is the reference schematic for GR5515IGND QFN56 package. Figure 4-1 Reference schematic for GR5515IGND QFN56 package Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 55 Reference Design Figure 4-2 is the reference schematic for GR5515IENDU QFN56 package. Figure 4-2 Reference schematic for GR5515IENDU QFN56 package Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 56 Reference Design Figure 4-3 is the reference schematic for GR5515I0NDA QFN56 package. Figure 4-3 Reference schematic for GR5515I0NDA package Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 57 Reference Design Figure 4-4 is the reference schematic for GR5515RGBD BGA68 package. Figure 4-4 Reference schematic for GR5515RGBD BGA68 package Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 58 Reference Design Figure 4-5 is the reference schematic for GR5515GGBD BGA55 package. Figure 4-5 Reference schematic for GR5515GGBD BGA55 package Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 59 Reference Design Figure 4-6 is the reference schematic for GR5513BEND QFN40 package. Figure 4-6 Reference schematic for GR5513BEND QFN40 package Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 60: Pcb Layout Reference Design

    RF route is not higher than 50 Ω, provide openings on the second layer, and use the third layer (PCB layer stackup: 0.6 mm, impedance: up to 50 Ω, as shown in Figure 4-8) as the reference plane. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 61 Details for the PCB layout reference design are provided below. Top layer This layer is used for component layout and routing of key signals such as RF. Figure 4-9 Top layer design for 4-layer PCB (QFN56) Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 62 Figure 4-11 L3 design for 4-layer PCB (QFN56) Bottom layer This layer is used for filter components layout and signal routing. Filter components should be as close to the corresponding IC pins as possible. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 63: Two-Layer Pcbs In Qfn Packages

    4-13, the top layer is used for component layout and routing of key signals such as RF), so that the bottom layer can be as complete as possible. Figure 4-13 Top layer design for 2-layer PCB Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 64: External Flash Connection For Gr5515I0Nda

    Flash shall be as close to the IC as possible to minimize the QSPI route. QSPI route lengths should be matched, with the tolerance within 50 mil. Figure 4-15 is a reference design for the PCB layout of GR5515I0NDA. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 65: Four-Layer Pcbs In Bga68 Package

    This is the reference ground plane for the ground return path of the 50 Ω RF transmission line. Two openings are provided underneath the signal output pads of the 32 MHz crystal on L2, to reduce the parasitic load capacitance of the crystal. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 66 Figure 4-18 L3 design for 4-layer PCB (BGA68) Bottom layer This layer is used for filter components layout and signal routes. Filter components should be as close to the corresponding IC pins as possible. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 67 Reference Design Figure 4-19 Bottom layer design for 4-layer PCB (BGA68) Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 68: Faq

    Smith chart from the vector network analyzer. However, for matching of other indicators (such as antenna gain and directionality), you are recommended to seek help from professional antenna factories. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 69: Glossary

    Queued Serial Peripheral Interface RoHS Restriction of Hazardous Substances Directive Software Development Kit System-on-Chip Serial Peripheral Interface SVHC Substance of Very High Concern Serial Wire Debug UART Universal Asynchronous Receiver/Transmitter Universal Serial Bus Crystal Oscillator Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 70: Appendix: Qfn And Bga Assembly Guideline

    GR551x, certain constraints are added to IPC’s methodology. The pad pattern developed here includes considerations for lead and package tolerances. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 71: Package Information

    GR551x QFN56, including GR5515IGND QFN56, GR5515IENDU QFN56, and GR5515I0NDA QFN56, is a 56-pin and 7 x 7 x 0.75 (mm) QFN package. It is qualified for MSL3. Table 7-1 QFN56 package information Parameter Value Unit Tolerance Package Size 7 x 7 ±0.1 mm Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 72 Note: Drawing is not to scale. Table 7-2 QFN56 package dimensions Dimensions in mm Dimensions in inch Symbol 0.700 0.750 0.800 0.028 0.030 0.032 0.000 0.020 0.050 0.000 0.001 0.002 0.550 0.022 Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 73: Bga68

    Package Size 5.3 x 5.3 ±0.1 mm BGA Ball Count Total Thickness 0.88 ±0.1 mm BGA Ball Pitch 0.50 Ball Diameter 0.25 Ball Height 0.18 Figure 7-4 below shows the BGA68 package outlines. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 74 0.035 0.039 0.130 0.180 0.230 0.005 0.007 0.009 0.650 0.700 0.750 0.026 0.028 0.030 0.140 0.170 0.200 0.006 0.007 0.008 5.200 5.300 5.400 0.205 0.209 0.213 5.200 5.300 5.400 0.205 0.209 0.213 Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 75: Bga55

    3.5 x 3.5 ±0.1 mm BGA Ball Count Total Thickness 0.60 ±0.05 mm BGA Ball Pitch 0.40 Ball Diameter 0.22 Ball Height 0.12 ±0.03 mm The figure below shows the BGA55 package outlines. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 76 Dimension in inch Symbol 0.550 0.600 0.650 0.022 0.024 0.026 0.090 0.120 0.150 0.004 0.005 0.006 0.435 0.475 0.505 0.017 0.019 0.020 0.350 REF. 0.014 REF. 0.125 REF. 0.005 REF. 3.500 0.138 Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 77: Qfn40

    QFN Pad Count Total Thickness 0.75 ±0.05 mm QFN Pad Pitch 0.40 Pad Width 0.20 ±0.05 mm Exposed Pad Size 3.7 x 3.7 ±0.1 mm The figure below shows the QFN40 package outlines. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 78 0.008 0.010 5.000 BSC. 0.197 BSC. 5.000 BSC. 0.197 BSC. 0.400 BSC. 0.016 BSC. 3.600 3.700 3.800 0.142 0.146 0.150 3.600 3.700 3.800 0.142 0.146 0.150 0.300 0.400 0.500 0.012 0.016 0.020 Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 79: Board Mounting Guideline

    Aspect ratio = W/T L and W are the aperture length and width, and T is stencil thickness. For optimum paste release, the area and aspect ratios should be greater than 0.66 and 1.5 respectively. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 80: Via Types And Solder Voiding

    Electroless nickel/Immersion gold (ENIG) • Immersion silver • Immersion gold Selection of a suitable finish will depend on end users’ requirements for board design, assembly process, handling/ storage, and cost. 7.2.2.2 PCB Materials Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 81: Smt Printing Process

    An optimized reflow process is the key to ensure successful lead-free assembly, high yield and long-term solder joint reliability. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.
  • Page 82 150°C – 200°C Preheat time (ts) 60 seconds – 180 seconds Time above TBL, 217°C (TL) 60 seconds – 150 seconds Time within 5°C of peak temperature (tp) 20 seconds – 40 seconds Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 83: Rework Guideline

    In most applications, QFN and BGA packages will be mounted on smaller, thinner, and denser PCBs that introduce further challenges due to handling and heating issues. Because reflow of adjacent parts is not desirable during Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 84: Component Removal

    The solvent is usually specific to the type of paste used in the original assembly and paste manufacturer’s recommendations should be followed. 7.4.3 Solder Paste Printing Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

  • Page 85: Component Placement

    Agency (ECHA) on October 28, 2008 Regulation (EC) No 1907/2006 concerning Registration, Evaluation, Authorisation and Restriction of Chemicals (REACH). 7.7 Halogen Free GR551x is compliant with BS EN 14582: 2007 in regards to halogens: fluorine, chlorine, bromine, and iodine content. Copyright © 2023 Shenzhen Goodix Technology Co., Ltd.

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